Please wait a minute...
Chin. Phys. B, 2013, Vol. 22(2): 027303    DOI: 10.1088/1674-1056/22/2/027303
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES Prev   Next  

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

Luo Xiao-Rong (罗小蓉), Wang Qi (王琦), Yao Guo-Liang (姚国亮), Wang Yuan-Gang (王元刚), Lei Tian-Fei (雷天飞), Wang Pei (王沛), Jiang Yong-Heng (蒋永恒), Zhou Kun (周坤), Zhang Bo (张波)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, China
Abstract  A high voltage (>600 V) integrable silicon-on-insulator (SOI) trench-type lateral insulated gate bipolar transistor (LIGBT) with a reduced cell-pitch is proposed. The LIGBT features multiple trenches (MTs): two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX). Firstly, the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si. Secondly, oxide trenches bring in multi-directional depletion, leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field (RESURF) effect. Both increase the breakdown voltage (BV). Thirdly, oxide trenches fold the drift region around the oxide trenches, leading to a reduced cell-pitch. Finally, the oxide trenches enhance the conductivity modulation, resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop (Von). The oxide trenches cause a low anode-cathode capacitance, which increases the switching speed and reduces the turn-off energy loss (Eoff). The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm, a Von of 1.03 V at 100 A/cm-2, a turn-off time of 250 ns and Eoff of 4.1×10-3 mJ. The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits, simplifying the fabrication processes.
Keywords:  silicon-on-insulator      lateral insulated gate bipolar transistor      conductivity modulation      breakdown voltage      trench  
Received:  31 May 2012      Revised:  09 July 2012      Accepted manuscript online: 
PACS:  73.40.Ty (Semiconductor-insulator-semiconductor structures)  
  73.61.Ng (Insulators)  
  73.90.+f (Other topics in electronic structure and electrical properties of surfaces, interfaces, thin films, and low-dimensional structures)  
Fund: Projects supported by the National Natural Science Foundation of China (Grant No. 61176069); the State Key Laboratory of Electronic Thin Films and Integrated Devices, China (Grant No. CXJJ201004); and the National Key Laboratory of Analog Integrated Circuit, China (Grant No. 9140C090304110C0905).
Corresponding Authors:  Luo Xiao-Rong     E-mail:  xrluo@uestc.edu.cn

Cite this article: 

Luo Xiao-Rong (罗小蓉), Wang Qi (王琦), Yao Guo-Liang (姚国亮), Wang Yuan-Gang (王元刚), Lei Tian-Fei (雷天飞), Wang Pei (王沛), Jiang Yong-Heng (蒋永恒), Zhou Kun (周坤), Zhang Bo (张波) A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch 2013 Chin. Phys. B 22 027303

[1] Baliga B J and Alder M S 1982 Electron Devices Meeting, December 13-15, 1982, San Francisco, USA, 26 264
[2] Motto E R and Donlon J F 2004 APEC, February 22-26, 2004, Anaheim, USA, p. 235
[3] Jeong H and Fossum J G 1988 Bipolar Circuits and Echnology Meeting, September 12-13, 1988, Minneapolis, USA, p. 107
[4] Luo X R, Zhang B and Li Z J 2007 Solid-State Electron. 51 493
[5] Luo X R, Li Z J, Zhang B and Fu D P 2008 IEEE Electron. Dev. Lett. 29 1395
[6] Luo X R, Zhang B and Li Z J 2007 IEEE Electron. Dev. Lett. 28 422
[7] Luo X R, Wang Y G, Deng H and Udrea F 2010 Chin. Phys. B 19 077306
[8] Hu S D, Li Z J and Zhang B 2009 Chin. Phys. B 18 315
[9] Hu S D, Li Z J, Zhang B and Luo X R 2010 Chin. Phys. B 19 037303
[10] Son W S, Sohn Y H and Choi S 2004 Microelectron. J. 35 393
[11] Fujishima N and Salama C 1997 IEDM, December 10-13, 1997, Washington, USA, p. 359
[12] Fujishima N, Sugi A and Salama C 2006 US Patent 7005352
[13] Varadarajan K R, Chow T P and Wang J 2007 Proc. IEEE ISPSD 2007 233
[14] Johnny K, Sin O and Wan C 1993 US Patent 5227653
[15] Kang X, Lu L, Wang X, Santi E, Hudgins J L, Palmer P R and Donlon J F 2003 Industry Applications Conference, October 12-16, Salt Lake City, USA, p. 892
[1] High performance carrier stored trench bipolar transistor with dual shielding structure
Jin-Ping Zhang(张金平), Hao-Nan Deng(邓浩楠), Rong-Rong Zhu(朱镕镕), Ze-Hong Li(李泽宏), and Bo Zhang(张波). Chin. Phys. B, 2023, 32(3): 038501.
[2] Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure
Kuiyuan Tian(田魁元), Yong Liu(刘勇), Jiangfeng Du(杜江锋), and Qi Yu(于奇). Chin. Phys. B, 2023, 32(1): 017306.
[3] Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress
Chenkai Zhu(朱晨凯), Linna Zhao(赵琳娜), Zhuo Yang(杨卓), and Xiaofeng Gu(顾晓峰). Chin. Phys. B, 2022, 31(9): 097303.
[4] Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure
Xinxin Zuo(左欣欣), Jiang Lu(陆江), Xiaoli Tian(田晓丽), Yun Bai(白云), Guodong Cheng(成国栋), Hong Chen(陈宏), Yidan Tang(汤益丹), Chengyue Yang(杨成樾), and Xinyu Liu(刘新宇). Chin. Phys. B, 2022, 31(9): 098502.
[5] A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance
Pei Shen(沈培), Ying Wang(王颖), and Fei Cao(曹菲). Chin. Phys. B, 2022, 31(7): 078501.
[6] Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench
Chunzao Wang(王春早), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2022, 31(4): 047304.
[7] Lateral β-Ga2O3 Schottky barrier diode fabricated on (-201) single crystal substrate and its temperature-dependent current-voltage characteristics
Pei-Pei Ma(马培培), Jun Zheng(郑军), Ya-Bao Zhang(张亚宝), Xiang-Quan Liu(刘香全), Zhi Liu(刘智), Yu-Hua Zuo(左玉华), Chun-Lai Xue(薛春来), and Bu-Wen Cheng(成步文). Chin. Phys. B, 2022, 31(4): 047302.
[8] Impact of STI indium implantation on reliability of gate oxide
Xiao-Liang Chen(陈晓亮), Tian Chen(陈天), Wei-Feng Sun(孙伟锋), Zhong-Jian Qian(钱忠健), Yu-Dai Li(李玉岱), and Xing-Cheng Jin(金兴成). Chin. Phys. B, 2022, 31(2): 028505.
[9] Modeling of high permittivity insulator structure with interface charge by charge compensation
Zhi-Gang Wang(汪志刚), Yun-Feng Gong(龚云峰), and Zhuang Liu(刘壮). Chin. Phys. B, 2022, 31(2): 028501.
[10] Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness
Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Chin. Phys. B, 2021, 30(6): 067303.
[11] Design and simulation of AlN-based vertical Schottky barrier diodes
Chun-Xu Su(苏春旭), Wei Wen(温暐), Wu-Xiong Fei(费武雄), Wei Mao(毛维), Jia-Jie Chen(陈佳杰), Wei-Hang Zhang(张苇杭), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), and Yue Hao(郝跃). Chin. Phys. B, 2021, 30(6): 067305.
[12] A super-junction SOI-LDMOS with low resistance electron channel
Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生). Chin. Phys. B, 2021, 30(5): 057303.
[13] Improved 4H-SiC UMOSFET with super-junction shield region
Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), Cheng-Hao Yu(于成浩), and Fei Cao(曹菲). Chin. Phys. B, 2021, 30(5): 058502.
[14] Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit
Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(4): 048503.
[15] Novel fast-switching LIGBT with P-buried layer and partial SOI
Haoran Wang(王浩然), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(2): 027302.
No Suggested Reading articles found!