A low specific on-resistance SOI MOSFET with dual gates and recessed drain
Luo Xiao-Rong (罗小蓉)a b, Luo Yin-Chun (罗尹春)b, Fan Ye (范叶)b, Hu Gang-Yi (胡刚毅)a, Wang Xiao-Wei (王骁玮)b, Zhang Zheng-Yuan (张正元)a, Fan Yuan-Hang (范远航)b, Cai Jin-Yong (蔡金勇)b, Wang Pei (王沛)b, Zhou Kun (周坤)b
a Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China; b State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Abstract A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce Ron,sp and maintain a high breakdown voltage (BV). The BV of 233 V and Ron,sp of 4.151 mΩ·cm2 (VGS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.
Fund: Projects supported by the National Natural Science Foundation of China (Grant No. 61176069); the Science Foundation from the State Key Laboratory of Electronic Thin Films and Integrated Devices (Grant No. CXJJ201004); and the Fund from the National Key Laboratory of Analog Integrated Circuit (Grant No. 9140C090304110C0905).
Corresponding Authors:
Luo Xiao-Rong
E-mail: xrluo@uestc.edu.cn
Cite this article:
Luo Xiao-Rong (罗小蓉), Luo Yin-Chun (罗尹春), Fan Ye (范叶), Hu Gang-Yi (胡刚毅), Wang Xiao-Wei (王骁玮), Zhang Zheng-Yuan (张正元), Fan Yuan-Hang (范远航), Cai Jin-Yong (蔡金勇), Wang Pei (王沛), Zhou Kun (周坤) A low specific on-resistance SOI MOSFET with dual gates and recessed drain 2013 Chin. Phys. B 22 027304
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