Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

doi:10.1088/1674-1056/abdda7

Abstract A novel terminal-optimized triple RESURF LDMOS (TOTR-LDMOS) is proposed and verified in a 0.25-μ bipolar-CMOS-DMOS (BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage (BV) and electrostatic discharge (ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse (TLP) tests, direct current (DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance (R_on,sp) of 6.99 Ω·mm². Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

Keywords: lateral double-diffused MOSFET (LDMOS) terminal-optimization breakdown voltage electrostatic discharge

Received: 28 October 2020
Revised: 07 January 2021
Accepted manuscript online: 20 January 2021

PACS:	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61504049), the China Postdoctoral Science Foundation (Grant No. 2016M600361), and the Fundamental Research Funds for the Central Universities, China (Grant No. JUSRP51510).

Corresponding Authors: Xiao-Feng Gu
E-mail: xgu@jiangnan.edu.cn

Cite this article:

Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰) Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness 2021 Chin. Phys. B 30 067303

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Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

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