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SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability |
| Jin-Ping Zhang(张金平)1,2,†, Wei Chen(陈伟)1, Zi-Xun Chen(陈子珣)1, and Bo Zhang(张波)1 |
1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
2 Chongqing Institute of Microelectronics Industry Technology, University of Electronic Science and Technology of China, Chongqing 401331, China |
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Abstract A novel silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) with a dual shield gate (DSG) and optimized junction field-effect transistor (JFET) layer (ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device's dynamic performance but also greatly enhances the safe operating area (SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET (Con-ATMOS), the specific on-resistance (Ron, sp) is significantly reduced at almost the same avalanche breakdown voltage (BVav). Moreover, the DSG structure brings about much smaller reverse transfer capacitance (Crss) and input capacitance (Ciss), which helps to reduce the gate-drain charge (Qgd) and gate charge (Qg). Therefore, the high frequency figure of merit (HFFOM) of Ron, sp· Qgd and Ron, sp· Qg for the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively. The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current (Id,sat) at a gate voltage (Vgs) of 15 V for the ODSG-TMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate (SG) at a large drain voltage. With the reduced Id,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.
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Received: 12 February 2023
Revised: 19 May 2023
Accepted manuscript online: 08 June 2023
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PACS:
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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73.40.Qv
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(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
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85.30.Tv
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(Field effect devices)
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51.50.+v
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(Electrical properties)
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| Fund: Project supported by the China Postdoctoral Science Foundation (Grant No. 2020M682607). |
Corresponding Authors:
Jin-Ping Zhang
E-mail: jinpingzhang@uestc.edu.cn
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Cite this article:
Jin-Ping Zhang(张金平), Wei Chen(陈伟), Zi-Xun Chen(陈子珣), and Bo Zhang(张波) SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability 2023 Chin. Phys. B 32 118502
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