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Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs |
| Shao-Hua Yang(杨少华)1,2, Zhan-Gang Zhang(张战刚)2,†, Zhi-Feng Lei(雷志锋)2, Yun Huang(黄云)2, Kai Xi(习凯)3, Song-Lin Wang(王松林)4,5, Tian-Jiao Liang(梁天骄)4,5, Teng Tong(童腾)4, Xiao-Hui Li(李晓辉)4, Chao Peng(彭超)2, Fu-Gen Wu(吴福根)1, and Bin Li(李斌)6 |
1 School of Physics and Optoeletronic Engineering, Guangdong University of Technology, Guangzhou 510006, China;
2 Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510370, China;
3 Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China;
4 Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China;
5 Spallation Neutron Source Science Center, Dongguan 523803, China |
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Abstract Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the "worst direction" corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.
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Received: 05 December 2021
Revised: 17 April 2022
Accepted manuscript online: 14 June 2022
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PACS:
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61.80.Hg
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(Neutron radiation effects)
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61.82.Fk
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(Semiconductors)
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85.40.-e
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(Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology)
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02.50.Ng
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(Distribution theory and Monte Carlo studies)
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| Fund: Project supported by the Key-Area Research and Development Program of Guangdong Province, China (Grant No. 2019B010145001), the National Natural Science Foundation of China (Grant Nos. 12075065 and 12175045), and the Applied Fundamental Research Project of Guangzhou City, China (Grant No. 202002030299). |
Corresponding Authors:
Zhan-Gang Zhang
E-mail: zhangangzhang@163.com
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Cite this article:
Shao-Hua Yang(杨少华), Zhan-Gang Zhang(张战刚), Zhi-Feng Lei(雷志锋), Yun Huang(黄云), Kai Xi(习凯), Song-Lin Wang(王松林), Tian-Jiao Liang(梁天骄), Teng Tong(童腾), Xiao-Hui Li(李晓辉), Chao Peng(彭超), Fu-Gen Wu(吴福根), and Bin Li(李斌) Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs 2022 Chin. Phys. B 31 126103
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