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Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology |
| Dong-Qing Li(李东青)1,2,3, Tian-Qi Liu(刘天奇)1,5, Pei-Xiong Zhao(赵培雄)1, Zhen-Yu Wu(吴振宇)4, Tie-Shan Wang(王铁山)3, and Jie Liu(刘杰)1,2,† |
1 Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China;
2 University of Chinese Academy of Sciences, Beijing 100049, China;
3 School of Physical Science and Technology, Lanzhou University, Lanzhou 730000, China;
4 National University of Defense Technology, Changsha 410000, China;
5 Tsinghua University, Beijing 100084, China |
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Abstract Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.
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Received: 27 September 2021
Revised: 15 November 2021
Accepted manuscript online:
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PACS:
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61.80.Az
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(Theory and models of radiation effects)
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61.80.Jh
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(Ion radiation effects)
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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| Fund: Project supported by the National Natural Science Foundation of China (Grant Nos.12035019,11690041,and 62004221). |
Corresponding Authors:
Jie Liu,E-mail:J.Liu@impcas.ac.cn
E-mail: J.Liu@impcas.ac.cn
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| About author: 2021-11-26 |
Cite this article:
Dong-Qing Li(李东青), Tian-Qi Liu(刘天奇), Pei-Xiong Zhao(赵培雄), Zhen-Yu Wu(吴振宇), Tie-Shan Wang(王铁山), and Jie Liu(刘杰) Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology 2022 Chin. Phys. B 31 056106
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