An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

doi:10.1088/1674-1056/24/4/047304

Abstract An ultra-low specific on-resistance (R_on,sp) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal-oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV) is proposed and investigated by simulation. There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS); the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The R_on,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and R_on,sp of 12.4 mΩ · cm² are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the R_on,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and R_on,sp.

Keywords: trench U-shaped gate specific on-resistance breakdown voltage

Received: 09 June 2014
Revised: 17 October 2014
Accepted manuscript online:

PACS:	73.40.Ty	(Semiconductor-insulator-semiconductor structures)
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079) and the Program for New Century Excellent Talents at the University of Ministry of Education of China (Grant No. NCET-11-0062).

Corresponding Authors: Luo Xiao-Rong
E-mail: xrluo@uestc.edu.cn

Cite this article:

Li Peng-Cheng (李鹏程), Luo Xiao-Rong (罗小蓉), Luo Yin-Chun (罗尹春), Zhou Kun (周坤), Shi Xian-Long (石先龙), Zhang Yan-Hui (张彦辉), Lv Meng-Shan (吕孟山) An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer 2015 Chin. Phys. B 24 047304

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An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

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