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Chin. Phys. B, 2021, Vol. 30(4): 048503    DOI: 10.1088/1674-1056/abcf45
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit

Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂)
1 Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China
Abstract  A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μ m, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μ m, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.
Keywords:  Si/SiC heterojunction      LDMOS      breakdown voltage      specific on-resistance  
Received:  01 September 2020      Revised:  20 October 2020      Accepted manuscript online:  01 December 2020
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  73.40.Lq (Other semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions)  
Fund: Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).
Corresponding Authors:  Corresponding author. E-mail: bxduan@163.com   

Cite this article: 

Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂) Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit 2021 Chin. Phys. B 30 048503

1 Yi B and Chen X B 2017 IEEE Trans. Power Electron. 32 551
2 Qiao M, Li Y F, Zhou X, Li Z J and Zhang B 2014 IEEE Electron Dev. Lett. 35 774
3 Shi L X, Jia K and Sun W F 2013 IEEE Trans. Electron Dev. 60 346
4 Wang Z, Lu M T, Zhou X, Wang J and Zhang B 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, pp. 1-2
5 Chen X B and Sin J 2001 IEEE Trans. Electron Dev. 48 1288
6 Yao J F, Deng Y, Guo Y F, Zhang Z Y, Zhang J and Zhang M L 2019 IEEE J. Electron Dev. Soc. 7 1055
7 Duan B X, Li M Z, Dong Z M, Wang Y D and Yang Y T 2019 IEEE Trans. Electron Dev. 66 4836
8 Chan C W, Li F, Sanchez A, Mawby P A and Gammon P M 2017 IEEE Trans. Electron Dev. 64 3713
9 Duan B X, Lv J M, Zhao Y H and Yang Y T 2018 Micro Nano Lett. 13 96
10 Jennings M, Amador P T, Guy O J, Hammond R, Burrows S, Peter G, Lodzinski M, James C and Mawby P 2008 Electrochem. Solid-State Lett. 11 H306
11 Araki R, Shimizu H, Kurumi T, Kinoshita H and Yoshimoto M 2011 International Meeting for Future of Electron Devices, Osaka, pp. 68-69
12 Saddow S E, Frewin C L, Nezafati M, Oliveros A, Afroz S, Register J, Reyes M and Thomas S 2014 IEEE 9th Nanotechnology Materials and Devices Conference (NMDC), Aci Castello pp. 49-53
13 Kukushkin S A and Osipov A V 2014 J. Phys. D: Appl. Phys. 47 313001
14 Amador P T, Jennings M, Davis M, James C, Mawby P, Vishal S and Grasby 2007 J. Appl. Phys. 102 014505
15 Duan B X, Yang X, Lv J M and Yang Y T 2018 IEEE Trans. Electron Dev. 65 3388
16 Duan B X, Huang Y J, Xing J Y and Yang Y T 2019 Micro Nano Lett. 14 1092
17 Appels J A and Vaes H M J 1979 International Electron Devices Meeting, Washington, USA, pp. 238-241
18 Huang Y S and Baliga B J 1991 Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, USA, pp. 27-30
19 Stupp E H, Colak S and Ni J 1981 International Electron Devices Meeting, Washington DC, USA, pp. 426-428
20 Peter G, Chan C W, Fan L, Farzan G, Trajkovic T, Vasantha P, Denis F and Valeria K 2017 Materials Science in Semiconductor Processing, Vol. 78, October 2017
21 Yukihiro S, Takamasa K, Shimizu, Hideo S, Hiroyuki K and Masahiro Y 2014 Mater. Sci. Forum 778 714
22 Amato M and Rumennik V 1985 International Electron Devices Meeting, USA, pp. 736-739
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