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Chin. Phys. B, 2020, Vol. 29(3): 038503    DOI: 10.1088/1674-1056/ab6960

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

Jia-Fei Yao(姚佳飞)1,2, Yu-Feng Guo(郭宇锋)1,2, Zhen-Yu Zhang(张振宇)1,2, Ke-Meng Yang(杨可萌)1,2, Mao-Lin Zhang(张茂林)1,2, Tian Xia(夏天)3
1 College of Electronic and Optical Engineering&College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing 210023, China;
2 National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing 210023, China;
3 School of Electrical Engineering, University of Vermont, Burlington, VT 05405, USA
Abstract  This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (Ron,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower Ron,sp compared to the SD device and HK device.
Keywords:  high-k dielectric      step doped silicon pillar      model      breakdown voltage  
Received:  17 October 2019      Revised:  16 December 2019      Accepted manuscript online: 
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61704084 and 61874059).
Corresponding Authors:  Yu-Feng Guo     E-mail:

Cite this article: 

Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天) Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars 2020 Chin. Phys. B 29 038503

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