Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal-oxide-semiconductor device with high-κ insulator

doi:10.1088/1674-1056/27/4/048502

Abstract

An improved vertical power double-diffused metal-oxide-semiconductor (DMOS) device with a p-region(P1) and high-κ insulator vertical double-diffusion metal-oxide-semiconductor (HKP-VDMOS) is proposed to achieve a better performance on breakdown voltage (BV)/specific on-resistance (R_on,sp) than conventional VDMOS with a high-κ insulator (CHK-VDMOS). The main mechanism is that with the introduction of the P-region, an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage. Due to the assisted depletion effect of this p-region, the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region. Meanwhile, based on the superposition of the depleted charges, a closed-form model for electric field/breakdown voltage is generally derived, which is in good agreement with the simulation result within 10% of error. An HKP-VDMOS device with a breakdown voltage of 600 V, a reduced specific on-resistance of 11.5 mΩ·cm² and a figure of merit (FOM) (BV²/R_on,sp) of 31.2 MW·cm^-2 shows a substantial improvement compared with the CHK-VDMOS device.

Keywords: superposition HKP-VDMOS breakdown voltage specific on-resistance

Received: 12 December 2017
Revised: 15 January 2018
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	77.55.df	(For silicon electronics)
	51.50.+v	(Electrical properties)

Fund:

Project supported by the National Natural Science Foundation of China (Grant No. 61404110) and the National Higher-education Institution General Research and Development Project, China (Grant No. 2682014CX097).

Corresponding Authors: Zhi-Gang Wang
E-mail: zhigangwang@swjtu.edu.cn

Cite this article:

Xue Chen(陈雪), Zhi-Gang Wang(汪志刚), Xi Wang(王喜), James B Kuo Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal-oxide-semiconductor device with high-κ insulator 2018 Chin. Phys. B 27 048502

[1]	Chen X B and Huang M M 2012 IEEE Trans. Electron Dev. 59 2430
[2]	Lyu X J and Chen X B 2013 IEEE Trans. Electron Dev. 60 1709
[3]	Yi B, Lin Z and Chen X 2014 Superlattices & Microstructures 75 278
[4]	Zhai D Y, Zhu J, Zhao Y, Cai Y F, Shi Y and Zheng Y L 2015 Chin. Phys. B 24 077201
[5]	Zhai D Y, Zhao Y, Cai Y F, Shi Y and Zheng Y D 2014 Acta Phys. Sin. 63 127201
[6]	Wang P, Luo X R, Jiang Y H, Wang Q, Zhou K, Wu L J, Wang X W, Cai J Y, Luo Y C, Fan Y, Hu X R, Fang Y H, Wei J and Zhang B 2013 Chin. Phys. B 22 027305
[7]	Fan J, Wang Z G, Zhang B and Luo X Y 2013 Chin. Phys. B 22 048501
[8]	Luo X R, Cai J Y, Fan Y, Fan Y H, Wang X W, Wei J, Jang Y H, Zhou K, Yin C, Zhang B, Li Z J and Hu G Y 2013 IEEE Trans. Electron Dev. 60 2840
[9]	Mao W, Wang H Y, Wang X F, Du M, Zhang J F, Zheng X F, Wang C, Ma X H, Zhang J C and Hao Y 2017 Chin. Phys. B 26 047306
[10]	Li W, Zheng Z, Wang Z G, Li P, Fu X J, He Z R, Liu F, Yang F, Xiang F and Liu L C 2017 Chin. Phys. B 26 017701
[11]	Naugarhiya A and Kondekar P N 2015 Superlattices & Microstructures 83 310
[12]	Huang M and Chen X 2015 Superlattices & Microstructures 88 244
[13]	Napoli E, Wang H and Udrea F 2008 IEEE Electron Dev. Lett. 29 249
[14]	Wang H, Napoli E and Udrea F 2009 IEEE Trans. Electron Devices 56 3175
[15]	Tamaki T, Nakazawa Y, Kanai H, Abiko Y, Ikegami Y, Ishikawa M, Wakimoto E, Yasuda T and Eguchi S 2011 IEEE International Symposium on Power Semiconductor Devices and ICS pp. 308-311
[16]	Baliga B J 2008 Fundamentals of power semiconductor devices (Beijing:Science Press) pp. 100-104
[17]	Duan B and Yang Y 2011 IET Micro & Nano Lett. 6 777
[18]	Naugarhiya A and Kondekar P N 2013 IEEE International Conference on Control, Automation, Robotics and Embedded Systems pp. 1-4
[19]	Zhou J, Huang C F, Cheng C H and Zhao F 2016 IEEE Trans. Electron Dev. 63 2255
[20]	Takahashi K, Kuribayashi H, Kawashima T, Wakimoto S, Mochizuki K and Nakazawa H 2006 IEEE International Symposium on Power Semiconductor Devices and Ic's. pp. 1-4
[21]	Wu L J, Zhang Z J, Song Y, Yang H, Hu L M and Yuan N 2017 Chin. Phys. B 26 027101

[1]	Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure Kuiyuan Tian(田魁元), Yong Liu(刘勇), Jiangfeng Du(杜江锋), and Qi Yu(于奇). Chin. Phys. B, 2023, 32(1): 017306.
[2]	A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance Pei Shen(沈培), Ying Wang(王颖), and Fei Cao(曹菲). Chin. Phys. B, 2022, 31(7): 078501.
[3]	Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench Chunzao Wang(王春早), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2022, 31(4): 047304.
[4]	Lateral β-Ga₂O₃ Schottky barrier diode fabricated on (-201) single crystal substrate and its temperature-dependent current-voltage characteristics Pei-Pei Ma(马培培), Jun Zheng(郑军), Ya-Bao Zhang(张亚宝), Xiang-Quan Liu(刘香全), Zhi Liu(刘智), Yu-Hua Zuo(左玉华), Chun-Lai Xue(薛春来), and Bu-Wen Cheng(成步文). Chin. Phys. B, 2022, 31(4): 047302.
[5]	Modeling of high permittivity insulator structure with interface charge by charge compensation Zhi-Gang Wang(汪志刚), Yun-Feng Gong(龚云峰), and Zhuang Liu(刘壮). Chin. Phys. B, 2022, 31(2): 028501.
[6]	Quantum metrology with coherent superposition of two different coded channels Dong Xie(谢东), Chunling Xu(徐春玲), and Anmin Wang(王安民). Chin. Phys. B, 2021, 30(9): 090304.
[7]	Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Chin. Phys. B, 2021, 30(6): 067303.
[8]	Design and simulation of AlN-based vertical Schottky barrier diodes Chun-Xu Su(苏春旭), Wei Wen(温暐), Wu-Xiong Fei(费武雄), Wei Mao(毛维), Jia-Jie Chen(陈佳杰), Wei-Hang Zhang(张苇杭), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), and Yue Hao(郝跃). Chin. Phys. B, 2021, 30(6): 067305.
[9]	A super-junction SOI-LDMOS with low resistance electron channel Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生). Chin. Phys. B, 2021, 30(5): 057303.
[10]	Improved 4H-SiC UMOSFET with super-junction shield region Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), Cheng-Hao Yu(于成浩), and Fei Cao(曹菲). Chin. Phys. B, 2021, 30(5): 058502.
[11]	Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(4): 048503.
[12]	Novel fast-switching LIGBT with P-buried layer and partial SOI Haoran Wang(王浩然), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(2): 027302.
[13]	Simulation study of high voltage GaN MISFETs with embedded PN junction Xin-Xing Fei(费新星), Ying Wang(王颖), Xin Luo(罗昕), Cheng-Hao Yu(于成浩). Chin. Phys. B, 2020, 29(8): 080701.
[14]	Variable-K double trenches SOI LDMOS with high-concentration P-pillar Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星). Chin. Phys. B, 2020, 29(5): 057701.
[15]	Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天). Chin. Phys. B, 2020, 29(3): 038503.

No Suggested Reading articles found!

Viewed

Full text

Abstract

Cited

Metrics
Related Articles

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal-oxide-semiconductor device with high-κ insulator

Cite this article:

Online attention