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Chin. Phys. B, 2022, Vol. 31(5): 058506    DOI: 10.1088/1674-1056/ac6013
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

Bo Wang(王博)1,2, Peng Ding(丁芃)2, Rui-Ze Feng(封瑞泽)2, Shu-Rui Cao(曹书睿)2, Hao-Miao Wei(魏浩淼)2, Tong Liu(刘桐)2, Xiao-Yu Liu(刘晓宇)2, Hai-Ou Li(李海鸥)1,†, and Zhi Jin(金智)2,‡
1 Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China;
2 High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract  A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain-source current (ID,max) and maximum extrinsic transconductance (gm,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (fMAX) by reducing drain output conductance (gds) and drain to gate capacitance (Cgd). In addition, further improvement of fMAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of Cgd to source to gate capacitance (Cgs) by extending drain-side recess length (Lrd). Compared with the single-recessed HEMTs, the fMAX of double-recessed offset gate HEMTs was increased by about 20%.
Keywords:  InP      HEMT      maximum oscillation frequency (fMAX)      double-recess      offset gate  
Received:  15 January 2022      Revised:  11 March 2022      Accepted manuscript online: 
PACS:  85.30.Tv (Field effect devices)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  85.30.-z (Semiconductor devices)  
Fund: This work is supported by the National Natural Science Foundation of China (Grant Nos.61874036,62174041,and 61434006),the Open Project of State Key Laboratory of ASIC and System (Grant No.KVH1233021),the Opening Foundation of the State Key Laboratory of Advanced Materials and Electronic Components (Grant No.FHR-JS-201909007),the Guangxi Innovation Research Team Project (Grant Nos.2018GXNSFGA281004 and 2018GXNSFBA281152),the Guangxi Innovation Driven Development Special Fund Project (Grant No.AA19254015),and the Guangxi Key Laboratory of Precision Navigation Technology and Application Project (Grant Nos.DH201906,DH202020,and DH202001).
Corresponding Authors:  Hai-Ou Li,E-mail:lihaiou@guet.edu.cn;Zhi Jin,E-mail:jinzhi@ime.ac.cn     E-mail:  lihaiou@guet.edu.cn;jinzhi@ime.ac.cn
About author:  2022-3-23

Cite this article: 

Bo Wang(王博), Peng Ding(丁芃), Rui-Ze Feng(封瑞泽), Shu-Rui Cao(曹书睿), Hao-Miao Wei(魏浩淼), Tong Liu(刘桐), Xiao-Yu Liu(刘晓宇), Hai-Ou Li(李海鸥), and Zhi Jin(金智) Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process 2022 Chin. Phys. B 31 058506

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