Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

doi:10.1088/1674-1056/26/8/087304

Abstract

In the process of high-k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO₂/HfO₂ gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

Keywords: high-k/metal gate multi deposition multi annealing stress-induced leakage current post deposition annealing

Received: 02 May 2017
Revised: 05 May 2017
Accepted manuscript online:

PACS:	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	77.55.D-
	85.30.Tv	(Field effect devices)

Fund:

Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA016501) and the National Natural Science Foundation of China (Grant No. 61306129).

Corresponding Authors: Wenwu Wang
E-mail: wangwenwu@ime.ac.cn

About author: 0.1088/1674-1056/26/8/

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Yanrong Wang(王艳蓉), Hong Yang(杨红), Hao Xu(徐昊), Weichun Luo(罗维春), Luwei Qi(祁路伟), Shuxiang Zhang(张淑祥), Wenwu Wang(王文武), Jiang Yan(闫江), Huilong Zhu(朱慧珑), Chao Zhao(赵超), Dapeng Chen(陈大鹏), Tianchun Ye(叶甜春) Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process 2017 Chin. Phys. B 26 087304

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Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

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