Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET

doi:10.1088/1674-1056/26/2/027101

Abstract A novel voltage-withstand substrate with high-K (HK, k>3.9, k is the relative permittivity) dielectric and low specific on-resistance (R_on,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS) is proposed in this paper. The high-K dielectric and highly doped interface N⁺-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (N_d) and reshape the electric field distribution. The highly doped N⁺-layer under the high-K dielectric acts as a low resistance path to reduce the R_on,sp. The new device with the high breakdown voltage (BV), the low R_on,sp, and the excellent figure of merit (FOM=BV²/R_on,sp) is obtained. The BV of HKLR LDMOS is 534 V, R_on,sp is 70.6 mΩ·cm², and FOM is 4.039 MW·cm^-2.

Keywords: LDMOS high-K dielectric highly doped N⁺-layer high voltage specific on-resistance

Received: 12 September 2016
Revised: 10 November 2016
Accepted manuscript online:

PACS:	71.10.-w	(Theories and models of many-electron systems)
	73.20.-r	(Electron states at surfaces and interfaces)
	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	73.40.Ty	(Semiconductor-insulator-semiconductor structures)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61306094), the Project of Hunan Provincial Education Department, China (Grant No.13ZA0089), the Introduction of Talents Project of Changsha University of Science & Technology, China (Grant No. 1198023), and the Construct Program of the Key Discipline in Hunan Province, China.

Corresponding Authors: Li-Juan Wu
E-mail: 305719669@qq.com

Cite this article:

Li-Juan Wu(吴丽娟), Zhong-Jie Zhang(章中杰), Yue Song(宋月), Hang Yang(杨航), Li-Min Hu(胡利民), Na Yuan(袁娜) Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET 2017 Chin. Phys. B 26 027101

[1]	Appels J A and Vaes H M J 1979 IEEE Electron Devices Meeting, 3-5 December, 1979, Washington, DC, USA, p. 238
[2]	Appels J, Collet M G, Hart P A H, Vaes H M J and Verhoeven J F C M 1980 Philips J. Res. 35 1
[3]	Vaes H M J and Appels J A 1980 IEEE Electron Devices Meeting, 8-10 December, 1980, Washington, DC, USA, p. 87
[4]	Wildi E J, Gray P V, Chow T P, Chang H R and Cornell M 1982 IEEE Electron Devices Meeting, 13-15 December, 1982, San Francisco, Ca, USA, p. 268
[5]	Ludikhuize A W 2000 Proc. 11th Int. Symp. Power Semiconductor Devices and IC's, 22-25 May, 2000, Toulouse, France, p. 11
[6]	Zhang B, Wang W L, Chen W J, Li Z H and Li Z J 2009 IEEE Electron Dev. Lett. 30 849
[7]	Li J H, Li P, Huo W R, Zhang G J, Zhai Y H and Chen X B 2011 IEEE Electron Dev. Lett. 32 1266
[8]	Luo X R, Jiang Y H, Zhou K, Wang P, Wang X W, Wang Q, Yao G L, Zhang B and Li Z J 2012 IEEE Electron Dev. Lett. 33 1042
[9]	Chen X B and Huang M M 2012 IEEE Trans. Electron Dev. 59 2430
[10]	Chen X B 2007 US Patent 7 230310 B2
[11]	Guo Y F, Yao J F, Zhang B, Lin H and Zhang C C 2015 IEEE Electron Dev. Lett. 36 262
[12]	Lyu X J and Chen X B 2013 IEEE Trans. Electron Dev. 60 1709
[13]	Luo X R, Lv M S, Yin C, Wei J, Zhou K, Zhao Z Y, Sun T, Zhang B and Li Z J 2016 IEEE Trans. Electron Dev. 63 3804
[14]	Li H and Chen X B 2015 IEEE 11th International Conference on ASIC (ASICON), 3-6 November, 2015, Chengdu, China
[15]	Varadarajan K R, Chow T P, Wang J, Liu R and Gonzalez F 2007 Proc. 19th Int. Symp. Power Semiconductor Devices and IC's, 27-31 May, 2007, Jeju, Korea, p. 233
[16]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B and Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[17]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y, Fan J, Wang Q, Ge R, Zhang B, Li Z J and Udrea F 2012 IEEE Trans. Electron Dev. 59 504

[1]	A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance Pei Shen(沈培), Ying Wang(王颖), and Fei Cao(曹菲). Chin. Phys. B, 2022, 31(7): 078501.
[2]	Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Chin. Phys. B, 2021, 30(6): 067303.
[3]	Design and simulation of AlN-based vertical Schottky barrier diodes Chun-Xu Su(苏春旭), Wei Wen(温暐), Wu-Xiong Fei(费武雄), Wei Mao(毛维), Jia-Jie Chen(陈佳杰), Wei-Hang Zhang(张苇杭), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), and Yue Hao(郝跃). Chin. Phys. B, 2021, 30(6): 067305.
[4]	A super-junction SOI-LDMOS with low resistance electron channel Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生). Chin. Phys. B, 2021, 30(5): 057303.
[5]	Improved 4H-SiC UMOSFET with super-junction shield region Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), Cheng-Hao Yu(于成浩), and Fei Cao(曹菲). Chin. Phys. B, 2021, 30(5): 058502.
[6]	Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(4): 048503.
[7]	Variable-K double trenches SOI LDMOS with high-concentration P-pillar Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星). Chin. Phys. B, 2020, 29(5): 057701.
[8]	Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天). Chin. Phys. B, 2020, 29(3): 038503.
[9]	Design and fabrication of 10-kV silicon-carbide p-channel IGBTs with hexagonal cells and step space modulated junction termination extension Zheng-Xin Wen(温正欣), Feng Zhang(张峰), Zhan-Wei Shen(申占伟), Jun Chen(陈俊), Ya-Wei He(何亚伟), Guo-Guo Yan(闫果果), Xing-Fang Liu(刘兴昉), Wan-Shun Zhao(赵万顺), Lei Wang(王雷), Guo-Sheng Sun(孙国胜), Yi-Ping Zeng(曾一平). Chin. Phys. B, 2019, 28(6): 068504.
[10]	Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate Qi Li(李琦), Zhao-Yang Zhang(张昭阳), Hai-Ou Li(李海鸥), Tang-You Sun(孙堂友), Yong-He Chen(陈永和), Yuan Zuo(左园). Chin. Phys. B, 2019, 28(3): 037201.
[11]	Improved performance of back-gate MoS₂ transistors by NH₃-plasma treating high-k gate dielectrics Jian-Ying Chen(陈建颖), Xin-Yuan Zhao(赵心愿), Lu Liu(刘璐), Jing-Ping Xu(徐静平). Chin. Phys. B, 2019, 28(12): 128101.
[12]	Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions Wei Mao(毛维), Hai-Yong Wang(王海永), Peng-Hao Shi(石朋毫), Xiao-Fei Wang(王晓飞), Ming Du(杜鸣), Xue-Feng Zheng(郑雪峰), Chong Wang(王冲), Xiao-Hua Ma(马晓华), Jin-Cheng Zhang(张进成), Yue Hao(郝跃). Chin. Phys. B, 2018, 27(4): 047305.
[13]	Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal-oxide-semiconductor device with high-κ insulator Xue Chen(陈雪), Zhi-Gang Wang(汪志刚), Xi Wang(王喜), James B Kuo. Chin. Phys. B, 2018, 27(4): 048502.
[14]	Improvement of reverse blocking performance in vertical power MOSFETs with Schottky-drain-connected semisuperjunctions Wei Mao(毛维), Hai-Yong Wang(王海永), Xiao-Fei Wang(王晓飞), Ming Du(杜鸣), Jin-Feng Zhang(张金风), Xue-Feng Zheng(郑雪峰), Chong Wang(王冲), Xiao-Hua Ma(马晓华), Jin-Cheng Zhang(张进成), Yue Hao(郝跃). Chin. Phys. B, 2017, 26(4): 047306.
[15]	Ultra-low specific on-resistance high-voltage vertical double diffusion metal-oxide-semiconductor field-effect transistor with continuous electron accumulation layer Da Ma(马达), Xiao-Rong Luo(罗小蓉), Jie Wei(魏杰), Qiao Tan(谭桥), Kun Zhou(周坤), Jun-Feng Wu(吴俊峰). Chin. Phys. B, 2016, 25(4): 048502.

No Suggested Reading articles found!

Viewed

Full text

Abstract

Cited

Metrics
Related Articles

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET

Cite this article:

Online attention