Please wait a minute...
Chin. Phys. B, 2015, Vol. 24(2): 028502    DOI: 10.1088/1674-1056/24/2/028502
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

Zhang Jun (张珺), Guo Yu-Feng (郭宇锋), Xu Yue (徐跃), Lin Hong (林宏), Yang Hui (杨慧), Hong Yang (洪洋), Yao Jia-Fei (姚佳飞)
College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
Abstract  A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.
Keywords:  SOI      RESURF      breakdown voltage      1D model  
Received:  23 June 2014      Revised:  04 September 2014      Accepted manuscript online: 
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  84.70.+p (High-current and high-voltage technology: power systems; power transmission lines and cables)  
Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61076073) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20133223110003).
Corresponding Authors:  Guo Yu-Feng     E-mail:  yfguo@njupt.edu.cn

Cite this article: 

Zhang Jun (张珺), Guo Yu-Feng (郭宇锋), Xu Yue (徐跃), Lin Hong (林宏), Yang Hui (杨慧), Hong Yang (洪洋), Yao Jia-Fei (姚佳飞) One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation 2015 Chin. Phys. B 24 028502

[1] Zhou H T, Zhou X and Benistant F 2014 Microelectronics Reliability 54 1096
[2] Cortés I, Toulon G, Morancho F, Hugonnard-Bruyere E, Villard B and Toren W J 2012 Microelectronics Reliability 52 503
[3] Imam M, Quddus M, Adams J and Hossain Z 2004 IEEE Trans. Electron. Dev. 51 141
[4] Appels J A and Vaes H M 1979 Proceedings of the 25th Electron Devices Meeting, December 3-5, 1979, Washington D C, USA, p. 238
[5] Hunag Y S and Baliga B J 1991 Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, April 22-24, 1991, Baltimore, USA, p. 27
[6] Yang W W, Cheng X H, Yu Y H, Song Z R and Shen D S 2005 Solid-State Electron. 49 43
[7] Fan J, Zhang B, Luo X R and Li Z J 2010 Proceedings of the 10th International Conference on Solid-State and Integrated Circuit Technology, November 1-4, 1991, Shanghai, China, p. 966
[8] Hu X R, Zhang B, Luo X R and Li Z J 2012 Solid-State Electron. 69 89
[9] Kim I, Matsumoto S, Sakai T and Yachi T 1995 Solid-State Electron. 39 95
[10] Chung S K, Han S Y, Shin J C, Choi Y I and Kim S B 1996 IEEE Electron. Dev. Lett. 17 22
[11] Hu S D, Luo J, Tan K Z, Zhang L, Li Z J, Zhang B, Zhou J L, Gan P, Qin G L and Zhang Z Y 2012 Microelectronics Reliability 52 692
[12] Chung S K and Han S Y 1998 IEEE Trans. Electron. Dev. 45 1374
[13] Chang Y H and Chang C H 2011 Microelectronics Reliability 51 2059
[14] Guo Y F, Li Z J and Zhang B 2006 Microelectron. J. 37 861
[15] Hu S D, Zhang B and Li Z J 2009 Chin. Phys. B 18 315
[16] Fan J, Zhang B, Luo X R and Li Z J 2013 Chin. Phys. B 22 118502
[1] Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure
Kuiyuan Tian(田魁元), Yong Liu(刘勇), Jiangfeng Du(杜江锋), and Qi Yu(于奇). Chin. Phys. B, 2023, 32(1): 017306.
[2] A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance
Pei Shen(沈培), Ying Wang(王颖), and Fei Cao(曹菲). Chin. Phys. B, 2022, 31(7): 078501.
[3] Lateral β-Ga2O3 Schottky barrier diode fabricated on (-201) single crystal substrate and its temperature-dependent current-voltage characteristics
Pei-Pei Ma(马培培), Jun Zheng(郑军), Ya-Bao Zhang(张亚宝), Xiang-Quan Liu(刘香全), Zhi Liu(刘智), Yu-Hua Zuo(左玉华), Chun-Lai Xue(薛春来), and Bu-Wen Cheng(成步文). Chin. Phys. B, 2022, 31(4): 047302.
[4] Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench
Chunzao Wang(王春早), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2022, 31(4): 047304.
[5] Modeling of high permittivity insulator structure with interface charge by charge compensation
Zhi-Gang Wang(汪志刚), Yun-Feng Gong(龚云峰), and Zhuang Liu(刘壮). Chin. Phys. B, 2022, 31(2): 028501.
[6] Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness
Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Chin. Phys. B, 2021, 30(6): 067303.
[7] Design and simulation of AlN-based vertical Schottky barrier diodes
Chun-Xu Su(苏春旭), Wei Wen(温暐), Wu-Xiong Fei(费武雄), Wei Mao(毛维), Jia-Jie Chen(陈佳杰), Wei-Hang Zhang(张苇杭), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), and Yue Hao(郝跃). Chin. Phys. B, 2021, 30(6): 067305.
[8] A super-junction SOI-LDMOS with low resistance electron channel
Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生). Chin. Phys. B, 2021, 30(5): 057303.
[9] Improved 4H-SiC UMOSFET with super-junction shield region
Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), Cheng-Hao Yu(于成浩), and Fei Cao(曹菲). Chin. Phys. B, 2021, 30(5): 058502.
[10] Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit
Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(4): 048503.
[11] Novel fast-switching LIGBT with P-buried layer and partial SOI
Haoran Wang(王浩然), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(2): 027302.
[12] Simulation study of high voltage GaN MISFETs with embedded PN junction
Xin-Xing Fei(费新星), Ying Wang(王颖), Xin Luo(罗昕), Cheng-Hao Yu(于成浩). Chin. Phys. B, 2020, 29(8): 080701.
[13] Variable-K double trenches SOI LDMOS with high-concentration P-pillar
Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星). Chin. Phys. B, 2020, 29(5): 057701.
[14] Role of remote Coulomb scattering on the hole mobility at cryogenic temperatures in SOI p-MOSFETs
Xian-Le Zhang(张先乐), Peng-Ying Chang(常鹏鹰), Gang Du(杜刚), Xiao-Yan Liu(刘晓彦). Chin. Phys. B, 2020, 29(3): 038505.
[15] Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars
Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天). Chin. Phys. B, 2020, 29(3): 038503.
No Suggested Reading articles found!