Dual-gate lateral double-diffused metal–oxide semiconductor with ultra-low specific on-resistance

doi:10.1088/1674-1056/22/4/048501

Abstract A new high voltage trench lateral double-diffused metal-oxide semiconductor (LDMOS) with ultra-low specific on-resistance (R_on,sp) is proposed. The structure features dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide dual conduction channel and reduce R_on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; Furthermore, R_on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Keywords: breakdown voltage specific on-resistance dual gate oxide trench

Received: 09 April 2012
Revised: 13 September 2012
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)
	84.70.+p	(High-current and high-voltage technology: power systems; power transmission lines and cables)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61176069), the National Key Laboratory of Analog Integrated Circuit, China (Grant No. 9140C090304110C0905), and the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices, China (Grant No. CXJJ201004).

Corresponding Authors: Fan Jie
E-mail: fan576@163.com

Cite this article:

Fan Jie (范杰), Wang Zhi-Gang (汪志刚), Zhang Bo (张波), Luo Xiao-Rong (罗小蓉) Dual-gate lateral double-diffused metal–oxide semiconductor with ultra-low specific on-resistance 2013 Chin. Phys. B 22 048501

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Dual-gate lateral double-diffused metal–oxide semiconductor with ultra-low specific on-resistance

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