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Chin. Phys. B, 2011, Vol. 20(10): 107101    DOI: 10.1088/1674-1056/20/10/107101
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES Prev   Next  

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

Wu Li-Juan(吴丽娟)a)b)† , Hu Sheng-Dong(胡盛东) c), Luo Xiao-Rong(罗小蓉)a), Zhang Bo(张波)a), and Li Zhao-Ji(李肇基) a)
a State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; b College of Communication Engineering, Chengdu University of Information Technology, Chengdu 610225, China; c College of Communication Engineering, Chongqing University, Chongqing 400044, China 
Abstract  A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (EI) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of EI and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
Keywords:  interface charges      breakdown voltage      partial-SOI      accumulation holes      self-heating effect  
Received:  02 November 2010      Revised:  21 February 2011      Accepted manuscript online: 
PACS:  71.10.-w (Theories and models of many-electron systems)  
  73.20.-r (Electron states at surfaces and interfaces)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  77.20.Jp  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721).

Cite this article: 

Wu Li-Juan(吴丽娟), Hu Sheng-Dong(胡盛东), Luo Xiao-Rong(罗小蓉), Zhang Bo(张波), and Li Zhao-Ji(李肇基) Partial-SOI high voltage P-channel LDMOS with interface accumulation holes 2011 Chin. Phys. B 20 107101

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