Please wait a minute...
Chin. Phys. B, 2010, Vol. 19(8): 087202    DOI: 10.1088/1674-1056/19/8/087202
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES Prev   Next  

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

Song Qing-Wen(宋庆文), Zhang Yu-Ming(张玉明), Zhang Yi-Men(张义门), Zhang Qian(张倩), and LÜ Hong-Liang(吕红亮)
School of Microelectronics, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China
Abstract  This paper proposes a double epi-layers 4H–SiC junction barrier Schottky rectifier (JBSR) with embedded P layer (EPL) in the drift region. The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process. The electric field and potential distribution are changed due to the buried P-layer, resulting in a high breakdown voltage (BV) and low specific on-resistance (Ron,sp). The influences of device parameters, such as the depth of the embedded P+ regions, the space between them and the doping concentration of the drift region, etc., on BV and Ron,sp are investigated by simulations, which provides a particularly useful guideline for the optimal design of the device. The results indicate that BV is increased by 48.5% and Baliga's figure of merit (BFOM) is increased by 67.9% compared to a conventional 4H–SiC JBSR.
Keywords:  junction barrier Schottky rectifier      4H–SiC      breakdown voltage      specific on-resistance  
Received:  19 October 2009      Revised:  03 March 2010      Accepted manuscript online: 
PACS:  84.30.Jc (Power electronics; power supply circuits)  
  61.72.S- (Impurities in crystals)  
  68.55.-a (Thin film structure and morphology)  
  73.30.+y (Surface double layers, Schottky barriers, and work functions)  
  84.70.+p (High-current and high-voltage technology: power systems; power transmission lines and cables)  
  85.30.De (Semiconductor-device characterization, design, and modeling)  
Fund: Project supported by the 13115 Innovation Engineering of Shaanxi Province of China (Grant No. 2008ZDKG-30).

Cite this article: 

Song Qing-Wen(宋庆文), Zhang Yu-Ming(张玉明), Zhang Yi-Men(张义门), Zhang Qian(张倩), and LÜ Hong-Liang(吕红亮) Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region 2010 Chin. Phys. B 19 087202

[1] Toru H, Tsutomu H, Jun S and Tsunenobu K 2008 IEEE Trans. Electron Devices 55 1841
[2] Cao Q J, Zhang Y M and Zhang Y M 2008 Chin. Phys. B 17 4622
[3] Sang-Cheol Kim, Wook Bahng, In-Ho Kang, Sung-Jae Joo and Nam-Kyun Kim 2008 Proc. 26th Int. Conf. on Microelectronics pp. 181–184
[4] Fujihira T 1997 Jpn. J. Appl. Phys. 36 6254
[5] Nishio Johji, Ota Chiharu, Hatakeyama Tetsuo, Shinohe Takashi, Kojima Kazutoshi, Nishizawa Shin-Ichi and Ohashi Hiromichi 2008 IEEE Trans. Electron Devices 45 1954
[6] Liang C Y and Kuang S 2008 IEEE Trans. Electron Devices 55 1961
[7] C'ezac N, Moranch F, Rossel P, Tranduc H and Peyre-Lavigne A 2000 Proc. 12th Int. Symp. Power Semicond. Devices ICs Toulouse France pp. 69–72
[8] Saitoh W, Omura I, Tokano K, Ogura T and Ohashi H 2002 14th Int. Sym. Power Semicond. Devices ICs pp. 33–36
[9] Chen X B, Wang X and Sin J K O 2000 IEEE Trans. Electron Devices 47 1280
[10] DESSIS-ISE, 2D Semiconductor Device Simulator version 10.0 2005 Integrated Systems Engineerin, Zurich
[11] Baliga B J 1989 IEEE Electron Device Lett. 10 455
[12] Chante J P, Locatelli M L, Planson D, Ottaviani L, Morvan E, Isoird K and Nallet F 1998 Proc CAS Int. Semicond. Conf. pp. 125–134
[13] Roschke M and Schwierz F 2001 IEEE Trans. Electron Devices 48 1442
[14] Jarrendahl K and Davis R F 1998 Semiconductors and Semimetals 52 1
[15] Zhu L, Chow T P, Jones K A and Agarwal A 2006 IEEE Trans. Electron Devices 53 363
[1] Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure
Kuiyuan Tian(田魁元), Yong Liu(刘勇), Jiangfeng Du(杜江锋), and Qi Yu(于奇). Chin. Phys. B, 2023, 32(1): 017306.
[2] A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance
Pei Shen(沈培), Ying Wang(王颖), and Fei Cao(曹菲). Chin. Phys. B, 2022, 31(7): 078501.
[3] Lateral β-Ga2O3 Schottky barrier diode fabricated on (-201) single crystal substrate and its temperature-dependent current-voltage characteristics
Pei-Pei Ma(马培培), Jun Zheng(郑军), Ya-Bao Zhang(张亚宝), Xiang-Quan Liu(刘香全), Zhi Liu(刘智), Yu-Hua Zuo(左玉华), Chun-Lai Xue(薛春来), and Bu-Wen Cheng(成步文). Chin. Phys. B, 2022, 31(4): 047302.
[4] Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench
Chunzao Wang(王春早), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2022, 31(4): 047304.
[5] Modeling of high permittivity insulator structure with interface charge by charge compensation
Zhi-Gang Wang(汪志刚), Yun-Feng Gong(龚云峰), and Zhuang Liu(刘壮). Chin. Phys. B, 2022, 31(2): 028501.
[6] Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness
Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Chin. Phys. B, 2021, 30(6): 067303.
[7] Design and simulation of AlN-based vertical Schottky barrier diodes
Chun-Xu Su(苏春旭), Wei Wen(温暐), Wu-Xiong Fei(费武雄), Wei Mao(毛维), Jia-Jie Chen(陈佳杰), Wei-Hang Zhang(张苇杭), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), and Yue Hao(郝跃). Chin. Phys. B, 2021, 30(6): 067305.
[8] A super-junction SOI-LDMOS with low resistance electron channel
Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生). Chin. Phys. B, 2021, 30(5): 057303.
[9] Improved 4H-SiC UMOSFET with super-junction shield region
Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), Cheng-Hao Yu(于成浩), and Fei Cao(曹菲). Chin. Phys. B, 2021, 30(5): 058502.
[10] Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit
Baoxing Duan(段宝兴), Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(4): 048503.
[11] Novel fast-switching LIGBT with P-buried layer and partial SOI
Haoran Wang(王浩然), Baoxing Duan(段宝兴), Licheng Sun(孙李诚), and Yintang Yang(杨银堂). Chin. Phys. B, 2021, 30(2): 027302.
[12] Simulation study of high voltage GaN MISFETs with embedded PN junction
Xin-Xing Fei(费新星), Ying Wang(王颖), Xin Luo(罗昕), Cheng-Hao Yu(于成浩). Chin. Phys. B, 2020, 29(8): 080701.
[13] Variable-K double trenches SOI LDMOS with high-concentration P-pillar
Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星). Chin. Phys. B, 2020, 29(5): 057701.
[14] Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars
Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天). Chin. Phys. B, 2020, 29(3): 038503.
[15] Breakdown voltage enhancement in GaN channel and AlGaN channel HEMTs using large gate metal height
Zhong-Xu Wang(王中旭), Lin Du(杜林), Jun-Wei Liu(刘俊伟), Ying Wang(王颖), Yun Jiang(江芸), Si-Wei Ji(季思蔚), Shi-Wei Dong(董士伟), Wei-Wei Chen(陈伟伟), Xiao-Hong Tan(谭骁洪), Jin-Long Li(李金龙), Xiao-Jun Li(李小军), Sheng-Lei Zhao(赵胜雷), Jin-Cheng Zhang(张进成), Yue Hao(郝跃). Chin. Phys. B, 2020, 29(2): 027301.
No Suggested Reading articles found!