Abstract A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35\mum 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.
Received: 29 December 2005
Revised: 12 June 2006
Accepted manuscript online:
Wang Yuan(王源), Jia Song(贾嵩), Chen Zhong-Jian(陈中建), and Ji Li-Jiu(吉利久) Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process 2006 Chinese Physics 15 2297
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