Design of a novel high holding voltage LVTSCR with embedded clamping diode

doi:10.1088/1674-1056/ab836e

Abstract In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p⁺ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p⁺ implant region and the n⁺ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5-7 V.

Keywords: electrostatic discharge silicon controlled rectifier clamping diode holding voltage

Received: 04 December 2019
Revised: 18 March 2020
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Mn	(Junction breakdown and tunneling devices (including resonance tunneling devices))
	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61504049) and the China Postdoctoral Science Foundation (Grant No. 2016M600361).

Corresponding Authors: Xiao-Feng Gu
E-mail: xgu@jiangnan.edu.cn

Cite this article:

Ling Zhu(朱玲), Hai-Lian Liang(梁海莲), Xiao-Feng Gu(顾晓峰), Jie Xu(许杰) Design of a novel high holding voltage LVTSCR with embedded clamping diode 2020 Chin. Phys. B 29 068503

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Design of a novel high holding voltage LVTSCR with embedded clamping diode

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