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Chin. Phys. B, 2015, Vol. 24(2): 028502    DOI: 10.1088/1674-1056/24/2/028502

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

Zhang Jun (张珺), Guo Yu-Feng (郭宇锋), Xu Yue (徐跃), Lin Hong (林宏), Yang Hui (杨慧), Hong Yang (洪洋), Yao Jia-Fei (姚佳飞)
College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
Abstract  A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.
Keywords:  SOI      RESURF      breakdown voltage      1D model  
Received:  23 June 2014      Revised:  04 September 2014      Accepted manuscript online: 
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  84.70.+p (High-current and high-voltage technology: power systems; power transmission lines and cables)  
Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61076073) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20133223110003).
Corresponding Authors:  Guo Yu-Feng     E-mail:

Cite this article: 

Zhang Jun (张珺), Guo Yu-Feng (郭宇锋), Xu Yue (徐跃), Lin Hong (林宏), Yang Hui (杨慧), Hong Yang (洪洋), Yao Jia-Fei (姚佳飞) One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation 2015 Chin. Phys. B 24 028502

[1] Zhou H T, Zhou X and Benistant F 2014 Microelectronics Reliability 54 1096
[2] Cortés I, Toulon G, Morancho F, Hugonnard-Bruyere E, Villard B and Toren W J 2012 Microelectronics Reliability 52 503
[3] Imam M, Quddus M, Adams J and Hossain Z 2004 IEEE Trans. Electron. Dev. 51 141
[4] Appels J A and Vaes H M 1979 Proceedings of the 25th Electron Devices Meeting, December 3-5, 1979, Washington D C, USA, p. 238
[5] Hunag Y S and Baliga B J 1991 Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, April 22-24, 1991, Baltimore, USA, p. 27
[6] Yang W W, Cheng X H, Yu Y H, Song Z R and Shen D S 2005 Solid-State Electron. 49 43
[7] Fan J, Zhang B, Luo X R and Li Z J 2010 Proceedings of the 10th International Conference on Solid-State and Integrated Circuit Technology, November 1-4, 1991, Shanghai, China, p. 966
[8] Hu X R, Zhang B, Luo X R and Li Z J 2012 Solid-State Electron. 69 89
[9] Kim I, Matsumoto S, Sakai T and Yachi T 1995 Solid-State Electron. 39 95
[10] Chung S K, Han S Y, Shin J C, Choi Y I and Kim S B 1996 IEEE Electron. Dev. Lett. 17 22
[11] Hu S D, Luo J, Tan K Z, Zhang L, Li Z J, Zhang B, Zhou J L, Gan P, Qin G L and Zhang Z Y 2012 Microelectronics Reliability 52 692
[12] Chung S K and Han S Y 1998 IEEE Trans. Electron. Dev. 45 1374
[13] Chang Y H and Chang C H 2011 Microelectronics Reliability 51 2059
[14] Guo Y F, Li Z J and Zhang B 2006 Microelectron. J. 37 861
[15] Hu S D, Zhang B and Li Z J 2009 Chin. Phys. B 18 315
[16] Fan J, Zhang B, Luo X R and Li Z J 2013 Chin. Phys. B 22 118502
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