Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored (CS) layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the carrier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop (V_on). In the off-state, due to the uniform carrier distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss (E_off). Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between E_off and V_on. Simulation results show that E_off of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same V_on of 1.1 V.