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Chin. Phys. B, 2016, Vol. 25(2): 027306    DOI: 10.1088/1674-1056/25/2/027306

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

Yan-Hui Zhang(张彦辉)1, Jie Wei(魏杰)1, Chao Yin(尹超)1, Qiao Tan(谭桥)1, Jian-Ping Liu(刘建平)1, Peng-Cheng Li(李鹏程)1, Xiao-Rong Luo(罗小蓉)1,2
1. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
2. Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China
Abstract  A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD>0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.
Keywords:  LDMOS      accumulation gate      back-side etching      breakdown voltage      specific on-resistance  
Received:  10 August 2015      Revised:  12 October 2015      Published:  05 February 2016
PACS:  73.40.Ty (Semiconductor-insulator-semiconductor structures)  
  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).
Corresponding Authors:  Xiao-Rong Luo     E-mail:

Cite this article: 

Yan-Hui Zhang(张彦辉), Jie Wei(魏杰), Chao Yin(尹超), Qiao Tan(谭桥), Jian-Ping Liu(刘建平), Peng-Cheng Li(李鹏程), Xiao-Rong Luo(罗小蓉) A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology 2016 Chin. Phys. B 25 027306

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