CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
Prev
Next
|
|
|
A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology |
Yan-Hui Zhang(张彦辉)1, Jie Wei(魏杰)1, Chao Yin(尹超)1, Qiao Tan(谭桥)1, Jian-Ping Liu(刘建平)1, Peng-Cheng Li(李鹏程)1, Xiao-Rong Luo(罗小蓉)1,2 |
1. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China; 2. Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China |
|
|
Abstract A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD>0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.
|
Received: 10 August 2015
Revised: 12 October 2015
Published: 05 February 2016
|
PACS:
|
73.40.Ty
|
(Semiconductor-insulator-semiconductor structures)
|
|
85.30.De
|
(Semiconductor-device characterization, design, and modeling)
|
|
85.30.Tv
|
(Field effect devices)
|
|
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079). |
Corresponding Authors:
Xiao-Rong Luo
E-mail: xrluo@uestc.edu.cn
|
Cite this article:
Yan-Hui Zhang(张彦辉), Jie Wei(魏杰), Chao Yin(尹超), Qiao Tan(谭桥), Jian-Ping Liu(刘建平), Peng-Cheng Li(李鹏程), Xiao-Rong Luo(罗小蓉) A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology 2016 Chin. Phys. B 25 027306
|
[1] |
Ludikhuize A W 2001 Proceedings of the 31 st European, IEEE Solid-State Device Research Conference, September 11-13, 2001, p. 35
|
[2] |
Iqbal M M, Udrea F and Napoli E 2009 IEEE Proceedings of the 21 st International Symposium on Power Semiconductor Devices and ICs, June 14-18, 2009, Barcelona, Spain, p. 247
|
[3] |
Ming Q, Li Y F, Zhou X, Li Z J and Zhang B 2014 IEEE Electron Dev. Lett. 35 774
|
[4] |
Chen X B U S Patent 5216275 [1993-06-01]
|
[5] |
Chen Y, Liang Y C, Samudra G S, Xin Y, Buddharaju K D and H H Feng 2008 IEEE Trans. Electron Dev. 55 211
|
[6] |
Luo X, Wei J, Shi X, Zhou K, Tian R, Zhang B and Li Z 2014 IEEE Trans. Electron Dev. 61 4304
|
[7] |
Merchant S, Arnold E, Baumgart H, Mukherjee S, Pein H and Pinker R 1991 IEEE Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, April 22-24, 1991, Maryland, USA, p. 31
|
[8] |
Luo X R, Wei J, Shi X L, Zhou K, Tian R C, Zhang B and Li Z J 2014 IEEE Trans. Electron. Dev. 61 4304
|
[9] |
Udrea F, Trajkovic T, Lee C, Garner D, Yuan X, Joyce J, Udugampola N, Bonnet G, Coulson D, Jacques R, Izmajlowicz M, van der Duijn Schouten N, Ansari Z, Moyse P and Amaratunga G A J 2005 IEEE Proceedings of the 17th International Symposium on Power Semiconductor Devices and ICs, Santa Barbara, USA, p. 267
|
[10] |
Leung Y K, Amit K P, Kenneth E G, James D P and Wong S S 1997 IEEE Electron Dev. Lett. 18 414
|
[11] |
Zhang S, Sin J K O, Lai T M L and Ko P K 1999 IEEE Trans. Electron Dev. 46 1036
|
[12] |
T Trajkovic, F Udrea, C Lee, N Udugampola, V Pathirana, A Mihaila and G A J Amaratunga 2008 IEEE Proceedings of the 20th International Symposium on Power Semiconductor Devices and ICs, May 18-22, 2008, Oralando, USA, p. 327
|
[13] |
Lyu X J and Chen X B 2013 IEEE Trans. Electron Dev. 60 3821
|
[14] |
Chen X B and Sin J K O 2001 IEEE Trans. Electron Dev. 48 344
|
[15] |
K P Gan, Yung C Liang, Ganesh S Samudra, S M Xu and Liu Y 2001 Power Electronics Specialists Conference, June 17-21, 2001, Vancouver, Canada, p. 2156
|
[16] |
Vestling L, Edholm B, Olsson J, Tiensuu S and Soderbarg A 1997 Proceedings of the International Symposium on Power Semiconductor Devices & IC's, May 26-29, 1997, Weimar, Germany, p. 45
|
[17] |
Wei J, Luo X, Zhang Y, Li P, Zhou K, Li Z and Zhang B 2015 Proceedings of the International Symposium on Power Semiconductor Devices and IC's, May 10-14, 2015, Hong Kong, China, p. 185
|
[18] |
Luo Y C, Luo X R, Hu G Y, Fan Y H, Li P C, Wei J, Tan Q and Zhang B 2014 Chin. Phys. B 23 077306
|
[19] |
Z Lin and X B Chen 2015 IEEE Electron Dev. Lett. 36 588
|
[20] |
Matsumura A, Sasaki T and Kitahara K US patent 0170940
|
|
[2003].
|
[21] |
Udrea F, Trajkovicand T and Amaratunga G A J 2004 Proceedings of IEEE Int. Electron Devices, December 13-15, 2004, San Francisco, USA, p. 451
|
[22] |
Udrea F and Amaratunga G US patent 6703684
|
|
[2004]
|
No Suggested Reading articles found! |
|
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
|
Shared |
|
|
|
|
|
Discussed |
|
|
|
|