For high voltage power metal–oxide–semiconductor field-effect transistors (MOSFETs), two major targets are to reduce the power dissipation and enhance the breakdown voltage (BV), thereby realizing the trade-off between the specific on-resistance (R_on,sp) and BV.^[1,2] Many approaches including the reduced surface field (RESURF) and super junction (SJ) are used to realize the targets. However, the R_on,sp in SJ and RESURF devices is strongly dependent on the drift doping concentration (N_d).^[3–6] In order to realize high BV for the thin SOI, the variable lateral doping (VLD) and back-side etching (BE) are typical technologies by achieving a uniform lateral electric field.^[7–9] However, the VLD technique leads to a “hot-spot” on the source side where the resistance is large for the low doping concentration^[10] and its fabrication process needs a long-time high-temperature annealing.^[11] The BE technique removes the substrate-assisted depletion effect (SAD), which results in a sharp decrease in N_d and restricts the current capability. Therefore, the BE technique was mainly applied to the IGBT with a conduction modulation effect.^[9,12]

In this paper, an ultra-thin SOI LDMOS with an accumulation gate (AG) over the drift region and back-side etching (BE) (AG-BE SOI LDMOS) is proposed. Except for complex external control circuits, a high density electron accumulation layer is formed along the drift surface in the on-state.^[13] This not only reduces the R_on,sp significantly, but also makes R_on,sp nearly independent of the doping concentration of the drift region. The BE technique allows a uniform doping concentration in the drift region to obtain high BV. The combination of the accumulation layer and the uniform doping concentration profile not only reduces the R_on,sp and the process difficulty, but also solves the “hot-spot” problem in the ultra-thin device with the VLD technology. The MEDICI simulator is used to study the mechanism of the AG-BE SOI LDMOS. The results demonstrate that the proposed device possesses good performances.

Figure 1 shows the schematic of the cross section of the AG-BE SOI LDMOS. The novel SOI LDMOS is characterized by the AG over the drift region and BE of the substrate. Note that the AG structure consists of a P-region and two diodes (D₁ and D₂) in series, and its two ends connect with the gate electrode and the drain electrode respectively. The substrate under the drift region is etched. The x and y directions are marked. L_d is the length of the drift region; t_top, t_si, and t_box represent the thickness values of the AG layer, the drift region and the buried oxide, respectively; N_d is the doping concentration of the drift region, and N_p is the doping concentration of the P– region in the AG structure.

Fig. 1.

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	Fig. 1. Schematic diagram of cross section of the AG-BE SOI LDMOS.

Figure 2 illustrates the operation mechanism of the novel SOI lateral-double-diffused metal-oxide-semiconductor. An MIS-like structure is formed by the N-drift region, the gate dielectric layer and the P- region of the AG structure. In the on-state with V_GD > 0, the diode D₁ principally sustains the gate-drain voltage (V_GD), and an electron accumulation layer is formed along the surface of the N-drift region. The accumulation layer forms an ultra-low resistance current path as shown in Fig. 2(a). Therefore, most of the current flows through the accumulation layer and thus the R_on,sp is almost independent of N_d. In the off-state, V_DS = V_DG > 0, the P- region of the AG and N-drift region works like an SJ with a thin oxide layer as depicted in Fig. 2(b). Then N_d increases and the R_on,sp further decreases due to the charge compensation.^[14,15] Note that the diode D₁ or D₂ is reverse-biased to sustain the gate-drain voltage drop (V_GD) in the on-state or off-state respectively, which ensures a lower leakage current in the top layer than that in Ref. [16].

Fig. 2.

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	Fig. 2. Operation mechanism. (a) On-state: VGS > Vth, VGD > 0, VDS > 0; (b) off-state: VDS > 0, VGS = 0, and reverse biased D2 sustains the VDG.

In our simulations, the physical models of CONSRH, AUGER, BGN, FLDMOB, SRFMOB, IMPACT.I, and CCSMOB are mainly used, and the NEWTON solution method is used with two types of carriers. The dimensional parameters of the novel structure are set as follows: L_d = 46 μm, t_top = t_si = 0.2 μm, and t_box = 1 μm.

Figure 3 shows the equipotential contours and the lateral component of surface electric field (E_x) for the AG-BE silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor, ultra-thin silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor with accumulation extended gate and VLD profile in drift region (AEG-VLD SOI LDMOS),^[17] ultra-thin silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor with VLD profile in drift region (VLD SOI LDMOS) and conventional ultra-thin silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor with a uniform doped drift region. For ultra-thin SOI devices in Figs. 3(a)–3(d), the structure with VLD or BE can generate near-ideal potential distributions in the drift region as shown in the red dashed boxes in Figs. 3(a)–3(c) respectively. The BE technique releases the equipotential lines below the buried oxide as shown in the black rectangle in Fig. 3(a); however, the equipotential contours of the VLD and AEG-VLD structure terminate in the bottom interface of the buried oxide as indicated in Figs. 3(b)–3(c). In other words, the BE removes the vertical voltage drop and avoids vertical premature breakdown, which indicates that the BV is almost independent of the thickness values of the drift region and the buried oxide. Figure 3(e) shows that E_x for the conventional device is zero in the middle, fortunately, the AG-BE or the VLD not only enhances the E_x but also makes the field distribution more uniform. Furthermore, the BE technique almost removes the electric field peak on the drain side (E_xd), and the AG enhances the E_x in the middle more effectively than the VLD. Therefore, the BV of the AG-BE silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor increases from 776 V to 818 V for the VLD silicon-on-insulator lateral-double-diffused metal-oxide-semiconductor.

Fig. 3.

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	Fig. 3. Equipotential contour distributions (20 V/contour) at breakdown (optimally) for (a) AG-BE SOI LDMOS (BV = 818 V), (b) AEG-VLD SOI LDMOS (BV = 800 V), (c) VLD SOI LDMOS (BV = 776 V), and (d) conventional SOI LDMOS (BV = 144 V); (e) lateral surface electric field component.

Figure 4 compares the on-state current densities of the AG-BE SOI LDMOS, the VLD SOI LDMOS and the JFP-BE SOI LDMOS at x = 5 μm. The JFP-BE SOI LDMOS features a junction field plate (JFP)^[18] and BE. In the blocking state, the P-region in the JFP generates additional depletion in the N-drift region and increases the N_d, which is almost the same as the scenarios in AG-BE devices, so the same optimal N_d = N_p = 4×10¹⁶ cm⁻³ and the same BV are obtained for the JFP-BE and AG-BE devices. For the AG-BE SOI LDMOS, the resistance in the drift region (R_D) contains the accumulation layer resistance (R_A) and the neutral drift region resistance (R_N) in parallel, and R_A ≪ R_N because of the high density accumulation electrons. Therefore, the surface current density of the accumulation layer is three orders higher than that in the neutral drift region, and the current through the accumulation layer (I_A) is approximately 88% of the total current (I_D) as shown in Fig. 4. Owing to the same N_d, the R_N of the AG-BE device is the same as that of the JFP-BE device, and thus the current density I_N values in the neutral drift region for AG-BE and JFP-BE devices are consistent. The I_N value of the VLD SOI LDMOS is higher than those of AG-BE and JFP-BE SOI LDMOS, because the SAD effect of the VLD SOI LDMOS allows a higher N_d. Consequently, compared with the cases of the other two devices, the R_on,sp of the AG-BE device drops significantly and is almost independent of N_d. The R_on,sp values of the AG-BE SOI LDMOS, the VLD SOI LDMOS, and the JFP-BE SOI LDMOS are 38.1 mΩ·cm², 106 mΩ·cm², and 191 mΩ·cm², respectively. However, the R_on,sp of SOI LDMOS only with the BE technique is over 5500 mΩ·cm² at the same cell pitch.

Fig. 4.

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	Fig. 4. Current density distributions of three devices at x = 5 μm.

Figures 5(a) and 5(b) show the three-dimensional (3D) temperature distributions of the AG-BE SOI LDMOS and the VLD SOI LDMOS at the same power density (P) of P = 1 mW/ μm, respectively. Obviously, the VLD SOI LDMOS suffers a serious “hot-spot” on the source side for the low doping concentration herein. By contrast, the AG-BE SOI LDMOS obtains a lower and more uniform temperature in the drift region due to the lower and more evenly-distributed R_D. Because of the accumulation layer and uniform drift doping, the maximum temperature of the AG-BE SOI LDMOS decreases from 359 K to 327 K of the VLD SOI LDMOS.

Fig. 5.

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	Fig. 5. 3D temperature distributions at P = 1 mW/ μm for (a) AG-BE SOI LDMOS and (b) VLD SOI LDMOS.

Figures 6(a) and 6(b), respectively, show the influences of the L_d and t_box on the BV and those of BV and R_on,sp on L_d for the AG-BE SOI LDMOS and VLD SOI LDMOS. As illustrated in Fig. 6(a), the BV of the VLD SOI LDMOS is saturated for L_d > 45 μm with t_box = 2 μm and L_d > 75 μm with t_box = 3 μm, because its vertical BV is limited by the thickness values of the drift region and the buried oxide layer. However, the BV of AG-BE SOI LDMOS is determined by the lateral BV and increases approximately linearly with increasing L_d, thereby avoiding the limit of the vertical BV as shown in Figs. 6(a) and 6(b). Therefore, the optimized t_box values for the novel device and the VLD SOI LDMOS are 1 μm and 3 μm, respectively. Moreover, owing to the accumulation layer, the R_on,sp of the novel device is lower and increases more slowly with the increasing L_d than that of VLD SOI LDMOS as shown in Fig. 6(b). Figure 7 compares the R_on,sp versus BV for this work with existing RESURF LDMOSFETs and SJ LDMOSFETs. The AG-BE SOI LDMOS obtains a superior trade-off between the BV and R_on,sp to the others.

Fig. 6.

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	Fig. 6. (a) Influences of Ld and tbox on BV, (b) dependences of the BV and Ron,sp on Ld.

Fig. 7.

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	Fig. 7. Comparison of results between this work and the others.

Figure 8 shows the feasible key fabrication steps of the AG-BE SOI LDMOS. The process to obtain the monocrystalline silicon in the AG is based on the SIMOX technology. Step (a) is for the process of the oxygen ion implantation,^[20] followed by the annealing process to form the field oxide layer, leaving monocrystalline silicon on the oxide. Step (b) is for boron implantation to form the P-region in AG. Steps (c) and (d) are to form the active region and P-well by etching and boron implantation. Steps (e)–(g) are for the processes to form the poly-gate, contact regions and electrodes respectively. Finally, front-passivation is accomplished and followed by a substrate back-etching and subsequent back-passivation.^[21,22]

Fig. 8.

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Fig. 8. Feasible key fabrication steps for forming the AG-BE SOI LDMOS: (a) oxygen ion implantation and annealing process to form the gate dielectric layer, (b) boron implantation to form the P-region in AG, (c) etching to form the active region, (d) boron implantation to form the P-well, (e) forming the gate oxide and poly-gate, (f) impurity implantation and annealing to form the contact regions, (g) forming the electrodes and front passivation, and (h) substrate back-etching and back passivation.

A novel SOI LDMOS with an accumulation gate and back-side etching is proposed and investigated by simulation. A high density electron accumulation layer generated by the AG provides a low resistant current path, which not only reduces the R_on,sp, but also flattens the surface temperature. On the other side, the back-side etching not only achieves a near-ideal potential distribution with a uniform doping concentration in the drift region but also avoids vertical premature breakdown. Compared with the VLD SOI LDMOS, the novel device combining the accumulation gate and back-side etching reduces the R_on,sp by 70.2% and improves the BV from 776 V to 818 V.