Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

doi:10.1088/1674-1056/20/2/028501

Abstract A low specific on-resistance (R_S,on) silicon-on-insulator (SOI) trench MOSFET (metal–oxide–semiconductor–field–effect–transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced R_S,on. Fourthly, the trench gate extended to the BOX further reduces R_S,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal–oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and R_S,on decreases from 419 mΩ·cm² to 36.6 mΩ·cm². The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

Keywords: silicon-on-insulator electric field breakdown voltage trench gate trench

Received: 19 September 2010
Revised: 12 October 2010
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)
	84.70.p

Fund: Projects supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the Science Fund of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices (Grant No. CXJJ201004).

Cite this article:

Luo Xiao-Rong(罗小蓉), Yao Guo-Liang(姚国亮), Chen Xi(陈曦), Wang Qi(王琦), Ge Rui(葛瑞), and Florin Udrea Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch 2011 Chin. Phys. B 20 028501

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Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

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