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Chin. Phys. B, 2021, Vol. 30(3): 038501    DOI: 10.1088/1674-1056/abd38f

New DDSCR structure with high holding voltage for robust ESD applications

Zi-Jie Zhou(周子杰)1,2, Xiang-Liang Jin(金湘亮)1,2,3,†, Yang Wang(汪洋)1,2, and Peng Dong(董鹏)4
1 School of Physics and Optoelectronics, Xiangtan University, Xiangtan 411105, China; 2 Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on a Chip, Xiangtan 411105, China; 3 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China; 4 Super-ESD Microelectronics Technology CO., LTD., Changsha 410100, China
Abstract  A novel dual direction silicon-controlled rectifier (DDSCR) with an additional P-type doping and gate (APGDDSCR) is proposed and demonstrated. Compared with the conventional low-voltage trigger DDSCR (LVTDDSCR) that has positive and negative holding voltages of 13.371 V and 14.038 V, respectively, the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device, respectively, and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for 12-V application. The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device, and the four-finger APGDDSCR can achieve positive and negative human-body model (HBM) protection capabilities of 22.281 kV and 23.45 kV, respectively, under 40-V voltage of core circuit failure, benefitting from the additional structure. The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage. Thus, a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage, it is equivalent to solving the non-uniform triggering problem of multi-finger device. The operating mechanism and the gate voltage are both discussed and verified in two-dimensional (2D) simulation and experiemnt.
Keywords:  dual direction silicon-controlled rectifier (DDSCR)      failure current      snapback gate voltage      simulation      transmission line pulsing (TLP)  
Received:  16 September 2020      Revised:  02 November 2020      Accepted manuscript online:  15 December 2020
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61774129, 61827812, and 61704145), the Huxiang High-level Talent Gathering Project from the Hunan Science and Technology Department, China (Grant No. 2019RS1037), and the Changsha Science and Technology Plan Key Projects, China (Grant Nos. kq1801035 and kq1703001).
Corresponding Authors:  Corresponding author. E-mail:   

Cite this article: 

Zi-Jie Zhou(周子杰), Xiang-Liang Jin(金湘亮), Yang Wang(汪洋), and Peng Dong(董鹏) New DDSCR structure with high holding voltage for robust ESD applications 2021 Chin. Phys. B 30 038501

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