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Chin. Phys. B, 2017, Vol. 26(7): 077303    DOI: 10.1088/1674-1056/26/7/077303

Analytical capacitance model for 14 nm FinFET considering dual-k spacer

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进)
Shanghai Key Laboratory of Multidimensional Information Processing and the Department of Electrical Engineering, East China Normal University, Shanghai 200241, China
Abstract  The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor (FinFET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the FinFET device with dual-k spacers.
Keywords:  fin field-effect transistor      parasitic capacitance model      conformal mapping      TCAD  
Received:  13 December 2016      Revised:  11 April 2017      Accepted manuscript online: 
PACS:  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  85.30.-z (Semiconductor devices)  
  77.55.df (For silicon electronics)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos.61574056 and 61204038) and the Natural Science Foundation of Shanghai,China (Grant No.14ZR1412000).
Corresponding Authors:  Xiao-Jin Li     E-mail:

Cite this article: 

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进) Analytical capacitance model for 14 nm FinFET considering dual-k spacer 2017 Chin. Phys. B 26 077303

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