Analytical capacitance model for 14 nm FinFET considering dual-k spacer

doi:10.1088/1674-1056/26/7/077303

Abstract The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor (FinFET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the FinFET device with dual-k spacers.

Keywords: fin field-effect transistor parasitic capacitance model conformal mapping TCAD

Received: 13 December 2016
Revised: 11 April 2017
Accepted manuscript online:

PACS:	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	85.30.-z	(Semiconductor devices)
	77.55.df	(For silicon electronics)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos.61574056 and 61204038) and the Natural Science Foundation of Shanghai,China (Grant No.14ZR1412000).

Corresponding Authors: Xiao-Jin Li
E-mail: xjli@ee.ecnu.edu.cn

Cite this article:

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进) Analytical capacitance model for 14 nm FinFET considering dual-k spacer 2017 Chin. Phys. B 26 077303

[1]	Guillorn M, Chang J, Bryant A, et al. 2008 Symposium on VLSI Technology, June 17–19, 2008, Honolulu, USA, p. 12
[2]	Liu F Y, Liu H Z, Liu B W and Guo Y F 2016 Chin. Phys. B 25 047305
[3]	Yu J T, Chen S M, Chen J J and Huang P C 2015 Chin. Phys. B 24 119401
[4]	Fan M M, Xu J P, Liu L, Bai Y R and Huang Y. 2015 Chin. Phys. B 24 037303
[5]	Sun L J, Shang G B Shang, Liu L L, Cheng J, Guo A, Ren Z, Hu S J, Chen S M, Zhao Y H, Chan M, Zhang L, Li X J and Shi Y L 2015 Solid. State. Electron 111 118
[6]	Pandey A, Kumar H, Manhas S K, Dasgupta S and Anand B 2016 IEEE Trans. Electron Devices 63 1392
[7]	Jeong E Y, Yoon J S, Baek C K, Kim Y R, Hong J H, Lee J S, Baek R H and Jeong Y H 2015 IEEE Trans. Electron Devices 62 3441
[8]	Khakifirooz A and Antoniadis D A 2006 International Electron Devices Meeting December 11–13, 2006, San Francisco, USA, p. 1
[9]	Pal P K, Kaushik B K and Dasgupta S 2015 IEEE Trans. Electron Devices 62 1105
[10]	Liu X, Jin X S and Lee J H 2009 Solid. State. Electron 53 1041
[11]	Lee K W, An T Y, Joo S Y, Kwon K W and Kim S Y 2013 IEEE Trans. Electron Devices 60 1786
[12]	Chauhan Y S, Lu D D and Sriramkumar V 2015 FinFET Modeling for IC Simulation and Design:Using the BSIM-CMG Standard (London:Academic Press) p. 157
[13]	Lacord J, Ghibaudo G and Boeuf F 2012 IEEE Trans. Electron Devices 59 1332
[14]	Lacord J, Martinie S, Rozeau O, Jaud M A, Barraud S and Barbé J C 2016 IEEE Trans. Electron Devices 63 781
[15]	Bansal A, Paul B C and Roy K 2006 IEEE Trans. Comput. Des. Integr. Circuits Syst. 25 2765
[16]	Synopsys Inc. Sentaurus TCAD manuals,[Online] Available:http://www.synopsys.com
[17]	Iwai H 2015 Solid. State. Electron. 112 56
[18]	Mark B 2014 Intel Developer Forum

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