Research on high-voltage 4H–SiC P–i–N diode with planar edge junction termination techniques

doi:10.1088/1674-1056/20/6/067102

Abstract The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H-SiC P-i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3×10^-5 A/cm².

Keywords: silicon carbide P-i-N diode junction termination technique simulation breakdown voltage

Received: 10 December 2010
Revised: 26 January 2011
Accepted manuscript online:

PACS:	71.20.Nr	(Semiconductor compounds)
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Kk	(Junction diodes)
	78.40.Fy	(Semiconductors)

Fund: Project supported by the Science and Technology Foundation of Hunan Province of China (Grant No. 2008FJ3102).

Cite this article:

Zhang Fa-Sheng (张发生), Li Xin-Ran (李欣然) Research on high-voltage 4H–SiC P–i–N diode with planar edge junction termination techniques 2011 Chin. Phys. B 20 067102

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Research on high-voltage 4H–SiC P–i–N diode with planar edge junction termination techniques

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