A novel power UMOSFET with a variable K dielectric layer

doi:10.1088/1674-1056/21/6/068503

Abstract A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on-state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Q_g ? R_ON and BV²/R_ON, as compared with the previous power UMOSFET.

Keywords: specific on-resistance power UMOSFET split gate variable K dielectric layer

Received: 24 October 2011
Revised: 11 November 2011
Accepted manuscript online:

PACS:	85.30.Tv	(Field effect devices)
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.-z	(Semiconductor devices)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 60906048), the Program for New Century Excellent Talents in University, China (Grant No. NCET-10-0052), and the Fundamental Research Funds for the Central Universities, China (Grant No. HEUCFT1008).

Corresponding Authors: Wang Ying
E-mail: wangying7711@yahoo.com

Cite this article:

Wang Ying(王颖), Lan Hao(兰昊), Cao Fei(曹菲), Liu Yun-Tao(刘云涛), and Shao Lei(邵雷) A novel power UMOSFET with a variable K dielectric layer 2012 Chin. Phys. B 21 068503

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A novel power UMOSFET with a variable K dielectric layer

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