Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

doi:10.1088/1674-1056/24/4/047303

Abstract A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal-oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Keywords: electrostatic discharge high holding voltage latch-up STSCR-LDMOS

Received: 05 August 2014
Revised: 06 November 2014
Accepted manuscript online:

PACS:	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Mn	(Junction breakdown and tunneling devices (including resonance tunneling devices))
	85.30.Rs	(Thyristors)

Corresponding Authors: Qiao Ming
E-mail: qiaoming@uestc.edu.cn

Cite this article:

Ma Jin-Rong (马金荣), Qiao Ming (乔明), Zhang Bo (张波) Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application 2015 Chin. Phys. B 24 047303

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Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

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