A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

doi:10.1088/1674-1056/21/6/068501

Abstract A low on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (R_on,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the R_on,sp. The BV and R_on,sp are 328 V and 8.8 mΩ·cm², respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces R_on,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Keywords: SOI electric field breakdown voltage trench gate specific on-resistance

Received: 23 September 2011
Revised: 17 November 2011
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)
	84.70.p

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060) and the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905).

Corresponding Authors: Luo Xiao-Rong
E-mail: xrluo@uestc.edu.cn

Cite this article:

Luo Xiao-Rong(罗小蓉), Yao Guo-Liang(姚国亮), Zhang Zheng-Yuan(张正元), Jiang Yong-Heng(蒋永恒), Zhou Kun(周坤), Wang Pei(王沛), Wang Yuan-Gang(王元刚), Lei Tian-Fei(雷天飞), Zhang Yun-Xuan(张云轩), and Wei Jie(魏杰) A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration 2012 Chin. Phys. B 21 068501

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A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

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