Hot-carrier degradation characteristics and explanation in 0.25μm PMOSFETs
Liu Hong-Xia (刘红侠)a, Hao Yue (郝跃)a, Hawkins I. D.b, Peaker A. R.b
a School of Microelectronics, Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China; b Centre for Electronic Materials, UMIST, PO Box 88,Manchester, M 60 1QD, UK
Abstract The hot-carrier effect (HCE) of deep-submicron PMOSFETs has been investigated. It is found that the HCE includes both generation of interface states and formation of positive fixed charges in the gate oxide. We present experimental evidences showing that two degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of positive fixed oxide charges is significant in the case of deep-submicron PMOSFETs, which degrades the threshold voltage and even limits the transistor lifetime. For advanced analogy and mixed signal applications, process and device reliability limits need to be set up based also on threshold voltage shift, in addition to traditional methods of the transconductance degradation or gate oxide lifetime. Secondly, the generation of interface states by holes influences the device characteristics. Some speculation on the HCE formation process is included.
Received: 17 September 2004
Revised: 24 January 2005
Accepted manuscript online:
(Semiconductor-device characterization, design, and modeling)
Fund: Project supported by the National Natural Science Foundation of China (Grant No 60206006) and the Key
Project of Chinese Ministry of Education (Grant No 104172).
Cite this article:
Liu Hong-Xia (刘红侠), Hao Yue (郝跃), Hawkins I. D., Peaker A. R. Hot-carrier degradation characteristics and explanation in 0.25μm PMOSFETs 2005 Chinese Physics 14 1644
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