High performance carrier stored trench bipolar transistor with dual shielding structure
Jin-Ping Zhang(张金平)1,2,†, Hao-Nan Deng(邓浩楠)1, Rong-Rong Zhu(朱镕镕)1, Ze-Hong Li(李泽宏)1, and Bo Zhang(张波)1
1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China(UESTC), Chengdu 610054, China; 2 Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan 523808, China
Abstract We propose a novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT). The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV), but also well reduces the gate-collector capacitance , gate charge , and turn-off loss of the device. Furthermore, lower turn-on loss and gate drive loss are also obtained. Simulation results show that with the same CS layer doping concentration cm, the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate () of 1 μm. Moreover, compared with the con-CSTBT, the at of 25 V and miller plateau charge () for the proposed DSS-CSTBT with of 1 μm are reduced by 79.4% and 74.3%, respectively. With the increases from 0 V to 15 V, the total for the proposed DSS-CSTBT with of 1 μm is reduced by 49.5%. As a result, at the same on-state voltage drop () of 1.55 V, the and are reduced from 20.3 mJ/cm and 19.3 mJ/cm for the con-CSTBT to 8.2 mJ/cm and 9.7 mJ/cm for the proposed DSS-CSTBT with of 1 μm, respectively. The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the and but also greatly reduces the .
Fund: Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB1201802), the Key Realm R&D Program of Guangdong Province, China (Grant No. 2018B010142001), and the Guangdong Basic and Applied Basic Research Foundation, China (Grant No. 2020A1515010128).
Jin-Ping Zhang(张金平), Hao-Nan Deng(邓浩楠), Rong-Rong Zhu(朱镕镕), Ze-Hong Li(李泽宏), and Bo Zhang(张波) High performance carrier stored trench bipolar transistor with dual shielding structure 2023 Chin. Phys. B 32 038501
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