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Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology |
| Chi Sun(孙驰)1,2, Linyuan Zhao(赵林媛)4, Tingting Hao(郝婷婷)1,2, Renrong Liang(梁仁荣)4,5, Haitao Ye(叶海涛)6, Junjie Li(李俊杰)1,2,3, and Changzhi Gu(顾长志)1,2,† |
1 Beijing National Laboratory for Condensed Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China;
2 School of Physical Sciences, CAS Key Laboratory of Vacuum Physics, University of Chinese Acdemy of Sciences, Beijing 100049, China;
3 Songshan Lake Materials Laboratory, Dongguan 523808, China;
4 Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
5 Beijing National Research Center for Information Science and Technology(BNRist), Tsinghua University, Beijing 100084, China;
6 Department of Engineering, University of Leicester, Leicester LE17 RH, U |
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Abstract Three-dimensional (3D) vertical architecture transistors represent an important technological pursuit, which have distinct advantages in device integration density, operation speed, and power consumption. However, the fabrication processes of such 3D devices are complex, especially in the interconnection of electrodes. In this paper, we present a novel method which combines suspended electrodes and focused ion beam (FIB) technology to greatly simplify the electrodes interconnection in 3D devices. Based on this method, we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al2O3 gate-oxide both grown by atomic layer deposition. Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires, which avoid cumbersome steps in the traditional 3D structure fabrication technology. Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V. The ON-current of the 2×2 pillars vertical channel transistor was 1.2 μA at the gate voltage of 3 V and drain voltage of 2 V, which can be also improved by increasing the number of pillars. Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.
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Received: 27 September 2021
Revised: 27 October 2021
Accepted manuscript online: 01 November 2021
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PACS:
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68.35.bg
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(Semiconductors)
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72.15.-v
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(Electronic conduction in metals and alloys)
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73.50.-h
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(Electronic transport phenomena in thin films)
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| Fund: Project supported by the National Key Research and Development Program of China (Grant Nos. 2016YFA0200400 and 2016YFA0200800), the National Natural Science Foundation of China (Grant Nos. 61888102, 12074420, and 11674387), Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDB33000000), and Key Research Program of Frontier Sciences, Chinese Acdemy of Sciences (Grant No. QYZDJ-SSWSLH042). |
Corresponding Authors:
Changzhi Gu
E-mail: czgu@iphy.ac.cn
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Cite this article:
Chi Sun(孙驰), Linyuan Zhao(赵林媛), Tingting Hao(郝婷婷), Renrong Liang(梁仁荣), Haitao Ye(叶海涛), Junjie Li(李俊杰), and Changzhi Gu(顾长志) Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology 2022 Chin. Phys. B 31 016801
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