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Chin. Phys. B, 2021, Vol. 30(5): 058101    DOI: 10.1088/1674-1056/abd749

Enhanced interface properties of diamond MOSFETs with Al2O3 gate dielectric deposited via ALD at a high temperature

Yu Fu(付裕)1, Rui-Min Xu(徐锐敏)1, Xin-Xin Yu(郁鑫鑫)2, Jian-Jun Zhou(周建军)2, Yue-Chan Kong(孔月婵)2, Tang-Sheng Chen(陈堂胜)2, Bo Yan(延波)1, Yan-Rong Li(李言荣)1,3, Zheng-Qiang Ma(马正强)4, and Yue-Hang Xu(徐跃杭)1,†
1 University of Electronic Science and Technology of China, Chengdu 611731, China;
2 Nanjing Electronic Devices Institute, Nanjing 210016, China;
3 Sichuan University, Chengdu 610041, China;
4 University of Wisconsin-Madison, Madison, WI 53705, USA
Abstract  The interface state of hydrogen-terminated (C-H) diamond metal-oxide-semiconductor field-effect transistor (MOSFET) is critical for device performance. In this paper, we investigate the fixed charges and interface trap states in C-H diamond MOSFETs by using different gate dielectric processes. The devices use Al$_{2}$O$_{3}$ as gate dielectrics that are deposited via atomic layer deposition (ALD) at 80 $^\circ$C and 300 $^\circ$C, respectively, and their $C$-$V$ and $I$-$V$ characteristics are comparatively investigated. Mott-Schottky plots ($1/C^{2}$-$V_{\rm G}$) suggest that positive and negative fixed charges with low density of about 10$^{11}$ cm$^{-2}$ are located in the 80-$^\circ$C- and 300-$^\circ$C deposition Al$_{2}$O$_{3}$ films, respectively. The analyses of direct current (DC)/pulsed $I$-$V$ and frequency-dependent conductance show that the shallow interface traps (0.46 eV-0.52 eV and 0.53 eV-0.56 eV above the valence band of diamond for the 80-$^\circ$C and 300-$^\circ$C deposition conditions, respectively) with distinct density ($7.8 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$-$8.5 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$ and $2.2 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$-$5.1 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$ for the 80-$^\circ$C- and 300-$^\circ$C-deposition conditions, respectively) are present at the Al$_{2}$O$_{3}$/C-H diamond interface. Dynamic pulsed $I$-$V$ and capacitance dispersion results indicate that the ALD Al$_{2}$O$_{3}$ technique with 300-$^\circ$C deposition temperature has higher stability for C-H diamond MOSFETs.
Keywords:  diamond MOSFET      ALD temperature      pulsed I-V      interface trap      conductance method  
Received:  05 October 2020      Revised:  26 November 2020      Accepted manuscript online:  30 December 2020
PACS: (Diamond)  
  85.30.Tv (Field effect devices)  
  85.30.De (Semiconductor-device characterization, design, and modeling)  
Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61922021), the National Key Research and Development Project, China (Grant No. 2018YFE0115500), and the Fund from the Sichuan Provincial Engineering Research Center for Broadband Microwave Circuit High Density Integration, China.
Corresponding Authors:  Yue-Hang Xu     E-mail:

Cite this article: 

Yu Fu(付裕), Rui-Min Xu(徐锐敏), Xin-Xin Yu(郁鑫鑫), Jian-Jun Zhou(周建军), Yue-Chan Kong(孔月婵), Tang-Sheng Chen(陈堂胜), Bo Yan(延波), Yan-Rong Li(李言荣), Zheng-Qiang Ma(马正强), and Yue-Hang Xu(徐跃杭) Enhanced interface properties of diamond MOSFETs with Al2O3 gate dielectric deposited via ALD at a high temperature 2021 Chin. Phys. B 30 058101

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