| CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
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A super-junction SOI-LDMOS with low resistance electron channel |
| Wei-Zhong Chen(陈伟中)1,2, Yuan-Xi Huang(黄元熙)1,†, Yao Huang(黄垚)1, Yi Huang(黄义)1, and Zheng-Sheng Han(韩郑生)2,3 |
1 College of Electronics Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, China;
2 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
3 University of Chinese Academy of Sciences, Beijing 100049, China |
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Abstract A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (Ron,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and Ron,sp of the device can reach 253 V and 15.5 mΩ·cm2, respectively, and the Baliga's figure of merit (FOM=BV2/Ron,sp) of 4.1 MW/cm2 is achieved, breaking through the silicon limit.
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Received: 07 December 2020
Revised: 18 January 2021
Accepted manuscript online: 05 February 2021
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PACS:
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73.40.Ty
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(Semiconductor-insulator-semiconductor structures)
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77.55.df
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(For silicon electronics)
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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51.50.+v
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(Electrical properties)
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Corresponding Authors:
Yuan-Xi Huang
E-mail: hyx115@126.com
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Cite this article:
Wei-Zhong Chen(陈伟中), Yuan-Xi Huang(黄元熙), Yao Huang(黄垚), Yi Huang(黄义), and Zheng-Sheng Han(韩郑生) A super-junction SOI-LDMOS with low resistance electron channel 2021 Chin. Phys. B 30 057303
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