Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

doi:10.1088/1674-1056/ab9de6

Abstract A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Keywords: electrostatic discharge (ESD) enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) modified lateral silicon-controlled rectifier (MLSCR) failure current holding voltage

Received: 29 March 2020
Revised: 21 May 2020
Accepted manuscript online: 18 June 2020

PACS:

85.30.De

(Semiconductor-device characterization, design, and modeling)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61874098 and 61974017) and the Fundamental Research Project for Central Universities, China (Grant No. ZYGX2018J025).

Corresponding Authors: Zhiwei Liu
E-mail: ziv_liu@hotmail.com

Cite this article:

Wenqiang Song(宋文强), Fei Hou(侯飞), Feibo Du(杜飞波), Zhiwei Liu(刘志伟), Juin J. Liou(刘俊杰) Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications 2020 Chin. Phys. B 29 098502

[1]	Ker M D and Hsu K C 2005 IEEE Trans. Dev. Mater. Rel. 5 235
[2]	Hou F H, Chen R B, Du F B, et al. 2019 Chin. Phys. B 28 088501
[3]	Zeng J, Dong S R, Liou J J, Han Y, Zhong L, Wang W 2015 IEEE Trans. Electron. Dev. 62 606
[4]	Sun R C, Wang Z X, Maxim K, Liang W, Liou J J and Liu D G 2015 IEEE Electron. Dev. Lett. 36 424
[5]	Liu Z W, Vinson J, Lou L F and Liou J J 2008 IEEE Electron. Dev. Lett. 29 360
[6]	Liu Z W, Liou J J, Dong S R and Han Y 2010 IEEE Electron. Dev. Lett. 31 845
[7]	Ma F, Zhang B, Han Y, Zheng J F, Song B, Dong S R, and Liang H L 2013 IEEE Electron. Dev. Lett. 34 1178
[8]	Liu Z W, Liou J J and Vinson J 2008 IEEE Electron. Dev. Lett. 29 753
[9]	Huang X Z, Liou J J, Liu Z W, Liu F, Liu J Z, and Cheng H 2016 IEEE Electron. Dev. Lett. 37 1311
[10]	Huang X Z, Liu Z W, Liu F, Liu J Z, and Song W Q 2017 Electron. Lett. 53 1274
[11]	Han Y, Song B, Dong S R, Li M L and Ma F 2010 Microelectronics Rel. 51 332
[12]	Liang H L, Xu Q, Zhu L, Gu X F, Sun G P, Lin F, Zhang S, Xiao K and Yu Z G 2018 IEEE Electron. Dev. Lett. 40 163
[13]	Cao S Q, Chun J H, Salman A A, Beebe S G and Dutton R W 2011 Microelectron. Reliab. 51 756
[14]	Jean R M, Pascal F, Charles-Alexandre L, Pascal N and Florence A 2009 Microelectron. Reliab. 49 1424
[15]	Parthasarathy S, Salcedo J A and Hajjar J 2013 Proceedings of the IEEE International Reliability Physics Symposium, April 14-18, 2013, Anaheim, USA, p. EL.5.1

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Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

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