Three-dimensional global interconnect based on a design window

doi:10.1088/1674-1056/20/10/108401

Abstract Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

Keywords: three-dimensional integrated circuit design window wiring resource bandwidth

Received: 29 May 2011
Revised: 21 June 2011
Accepted manuscript online:

PACS:	84.30.-r	(Electronic circuits)
	84.30.Bv	(Circuit theory)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009) and the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005).

Cite this article:

Qian Li-Bo(钱利波), Zhu Zhang-Ming(朱樟明), and Yang Yin-Tang(杨银堂) Three-dimensional global interconnect based on a design window 2011 Chin. Phys. B 20 108401

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Three-dimensional global interconnect based on a design window

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