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Chin. Phys. B, 2015, Vol. 24(6): 060503    DOI: 10.1088/1674-1056/24/6/060503
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Study on a new chaotic bitwise dynamical system and its FPGA implementation

Wang Qian-Xue (王倩雪)a, Yu Si-Min (禹思敏)a, C. Guyeuxb, J. Bahib, Fang Xiao-Le (方晓乐)c
a College of Automation, Guangdong University of Technology, Guangzhou 510006, China;
b Femto-st Institute, University of Franche-Comte, Besancon 25000, France;
c Land and Resources Technology Center of Guangdong Province, Guangzhou 510075, China
Abstract  In this paper, the structure of a new chaotic bitwise dynamical system (CBDS) is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathematically proven according to the Devaney's definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.
Keywords:  chaos      chaotic bitwise dynamical systems      FPGA implementation  
Received:  02 December 2014      Revised:  09 January 2015      Accepted manuscript online: 
PACS:  05.45.-a (Nonlinear dynamics and chaos)  
Fund: Project supported by China Postdoctoral Science Foundation (Grant No. 2014M552175), the Scientific Research Foundation for the Returned Overseas Chinese Scholars, Chinese Education Ministry, the National Natural Science Foundation of China (Grant No. 61172023), and the Specialized Research Foundation of Doctoral Subjects of Chinese Education Ministry (Grant No. 20114420110003).
Corresponding Authors:  Wang Qian-Xue     E-mail:
About author:  05.45.-a

Cite this article: 

Wang Qian-Xue (王倩雪), Yu Si-Min (禹思敏), C. Guyeux, J. Bahi, Fang Xiao-Le (方晓乐) Study on a new chaotic bitwise dynamical system and its FPGA implementation 2015 Chin. Phys. B 24 060503

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