| INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY |
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Back-side stress to ease p-MOSFET degradation on e-MRAM chips |
| Zhi-Meng Yu(于志猛)1,2,†, Xiao-Lei Yang(杨晓蕾)2,†, Xiao-Nan Zhao(赵晓楠)2, Yan-Jie Li(李艳杰)2, Shi-Kun He(何世坤)2,‡, and Ye-Wu Wang(王业伍)1,§ |
1 Department of Physics, Zhejiang Province Key Laboratory of Quantum Technology and Device & State Key Laboratory of Silicon Materials, Zhejiang University, Hangzhou 310027, China;
2 Zhejiang Hikstor Technology Co., Ltd., Hangzhou 311300, China |
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Abstract The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal-oxide-silicon field-effect transistors, especially on p-type devices. Herein, a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress. Through the deposition of tensile material on the back side, positive charges generated by silicon-hydrogen bond breakage were inhibited, resulting in a potential reduction in threshold voltage shift by up to 20%. In addition, it was found that the method could only relieve silicon-hydrogen bond breakage physically, thus failing to provide a complete cure. However, it holds significant potential for applications where additional thermal budget is undesired. Furthermore, it was also concluded that the method used in this work is irreversible, with its effect sustained to the chip package phase, and it ensures competitive reliability of the resulting magnetic tunnel junction devices.
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Received: 04 July 2024
Revised: 19 August 2024
Accepted manuscript online: 18 September 2024
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PACS:
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85.40.-e
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(Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology)
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81.05.-t
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(Specific materials: fabrication, treatment, testing, and analysis)
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42.82.Cr
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(Fabrication techniques; lithography, pattern transfer)
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| Fund: Project supported by the National Natural Science Foundation of China (Grant No. 51672246), the National Key Research and Development Program of China (Grant Nos. 2017YFA0304302 and 2020AAA0109003), and the Key Research and Development Program of Zhejiang Province, China (Grant No. 2021C01002). |
Corresponding Authors:
Shi-Kun He, Ye-Wu Wang
E-mail: he_shikun@hikstor.com;yewuwang@zju.edu.cn
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Cite this article:
Zhi-Meng Yu(于志猛), Xiao-Lei Yang(杨晓蕾), Xiao-Nan Zhao(赵晓楠), Yan-Jie Li(李艳杰), Shi-Kun He(何世坤), and Ye-Wu Wang(王业伍) Back-side stress to ease p-MOSFET degradation on e-MRAM chips 2024 Chin. Phys. B 33 128503
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