Abstract The speed performance and static power dissipation of the ultra-thin-body (UTB) MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width ($L_{\rm sp})$ and silicon film thickness $(t_{\rm si})$ are two independent parameters that influence the speed and static power dissipation of UTB silicon-on-insulator (SOI) MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of $t_{\rm si}$ and $L_{\rm sp}$ for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.
Received: 06 September 2006
Revised: 05 January 2007
Accepted manuscript online:
(Semiconductor-device characterization, design, and modeling)
Fund: Project supported by the
National Natural Science Foundation of China (Grant No~60625403), the State
Key Development Program for Basic Research of China
(Grant No~2006CB302701).
Cite this article:
Tian Yu(田豫), Huang Ru(黄如), Zhang Xing(张兴), and Wang Yang-Yuan(王阳元) Tradeoff between speed and static power dissipation of ultra-thin body SOI MOSFETs 2007 Chinese Physics 16 1743
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