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Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch
罗小蓉, 姚国亮, 陈曦, 王琦, 葛瑞, Florin Udrea
2011 (2):
28501-028501.
doi: 10.1088/1674-1056/20/2/028501
摘要
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A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal--oxide--semiconductor--field--effect--transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal--oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μ m, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.
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