Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs
Shurui Cao(曹书睿)1,2, Ruize Feng(封瑞泽)1,2, Bo Wang(王博)1,3, Tong Liu(刘桐)1,2, Peng Ding(丁芃)1,2,†, and Zhi Jin(金智)1,2,‡
1 High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; 2 University of Chinese Academy of Sciences, Beijing 100029, China; 3 Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China
Abstract A set of 100-nm gate-length InP-based high electron mobility transistors (HEMTs) were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, fT decreased while fmax increased, and the highest fmax of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usages.
Shurui Cao(曹书睿), Ruize Feng(封瑞泽), Bo Wang(王博), Tong Liu(刘桐), Peng Ding(丁芃), and Zhi Jin(金智) Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs 2022 Chin. Phys. B 31 058502
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