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Chin. Phys. B, 2015, Vol. 24(12): 128101    DOI: 10.1088/1674-1056/24/12/128101
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

Ma Liu-Hong (马刘红), Han Wei-Hua (韩伟华), Wang Hao (王昊), Yang Xiang (杨香), Yang Fu-Hua (杨富华)
Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
Abstract  We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm2·V-1·s-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si-SiO2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
Keywords:  junctionless nanowire transistors      trap      femtosecond laser lithography      electron mobility  
Received:  05 May 2015      Revised:  21 August 2015      Accepted manuscript online: 
PACS:  81.07.Gf (Nanowires)  
  73.63.-b (Electronic transport in nanoscale materials and structures)  
  73.40.-c (Electronic transport in interface structures)  
  85.30.Tv (Field effect devices)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126) and the National Basic Research Program of China (Grant No. 2010CB934104).
Corresponding Authors:  Han Wei-Hua, Yang Fu-Hua     E-mail:  weihua@semi.ac.cn;fhyang@semi.ac.cn

Cite this article: 

Ma Liu-Hong (马刘红), Han Wei-Hua (韩伟华), Wang Hao (王昊), Yang Xiang (杨香), Yang Fu-Hua (杨富华) Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors 2015 Chin. Phys. B 24 128101

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