Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

doi:10.1088/1674-1056/20/1/018502

Abstract The base–collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector–base bias–and shows a kink as the reverse collector–base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

Keywords: depletion capacitance heterojunction bipolar transistors thin film silicon on insulator SiGe

Received: 31 July 2010
Revised: 13 August 2010
Accepted manuscript online:

PACS:	85.30.Pq	(Bipolar transistors)
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.-z	(Semiconductor devices)

Fund: Project supported by the National Ministries and Commissions (Grant Nos. 51308040203, 72105499, and 6139801).

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Xu Xiao-Bo(徐小波), Zhang He-Ming(张鹤鸣), Hu Hui-Yong(胡辉勇), Ma Jian-Li(马建立), and Xu Li-Jun(许立军) Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator 2011 Chin. Phys. B 20 018502

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Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

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