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A novel low-swing interconnect optimization model with delay and bandwidth constraints |
| Zhu Zhang-Ming(朱樟明)†, Hao Bao-Tian(郝报田), Yang Yin-Tang(杨银堂), and Li Yue-Jin(李跃进) |
| Microelectronics School, Xidian University, Xi'an 710071, China |
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Abstract Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
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Received: 27 February 2010
Revised: 09 April 2010
Accepted manuscript online:
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PACS:
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84.30.-r
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(Electronic circuits)
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85.30.Tv
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(Field effect devices)
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| Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260), and the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005). |
Cite this article:
Zhu Zhang-Ming(朱樟明), Hao Bao-Tian(郝报田), Yang Yin-Tang(杨银堂), and Li Yue-Jin(李跃进) A novel low-swing interconnect optimization model with delay and bandwidth constraints 2010 Chin. Phys. B 19 127805
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