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Chin. Phys. B, 2014, Vol. 23(11): 117303    DOI: 10.1088/1674-1056/23/11/117303

Effect of gate length on the parameter degradation relations of PMOSFET under NBTI stress

Cao Yan-Rong (曹艳荣)a b, He Wen-Long (何文龙)a, Cao Cheng (曹成)a, Yang Yi (杨毅)a, Zheng Xue-Feng (郑雪峰)b, Ma Xiao-Hua (马晓华)c, Hao Yue (郝跃)b
a School of Mechano-electric Engineering, Xidian University, Xi'an 710071, China;
b Key Lab of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China;
c School of Technical Physics, Xidian University, Xi'an 710071, China
Abstract  The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature instability (NBTI) stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than 1 to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.
Keywords:  negative bias temperature instability (NBTI)      gate length      degradation  
Received:  02 April 2014      Revised:  14 May 2014      Accepted manuscript online: 
PACS:  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  85.30.Tv (Field effect devices)  
Fund: Project supported by the National Basic Research Program of China (Grant No. 2011CBA00606), the National Natural Science Foundation of China (Grant Nos. 61334002, 61106106, and 61176130), and the Fundamental Research Fund for the Central Universities of China (Grant No. JB140415).
Corresponding Authors:  Cao Yan-Rong     E-mail:

Cite this article: 

Cao Yan-Rong (曹艳荣), He Wen-Long (何文龙), Cao Cheng (曹成), Yang Yi (杨毅), Zheng Xue-Feng (郑雪峰), Ma Xiao-Hua (马晓华), Hao Yue (郝跃) Effect of gate length on the parameter degradation relations of PMOSFET under NBTI stress 2014 Chin. Phys. B 23 117303

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