Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs
Ruize Feng(封瑞泽)1,2, Bo Wang(王博)1,3, Shurui Cao(曹书睿)1,2, Tong Liu(刘桐)1, Yongbo Su(苏永波)1,2, Wuchang Ding(丁武昌)1,2, Peng Ding(丁芃)1,2,†, and Zhi Jin(金智)1,2,‡
1 High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; 2 University of Chinese Academy of Sciences, Beijing 100029, China; 3 Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China
Abstract We fabricated a set of symmetric gate-recess devices with gate length of 70nm. We kept the source-to-drain spacing () unchanged, and obtained a group of devices with gate-recess length from 0.4m to 0.8m through process improvement. In order to suppress the influence of the kink effect, we have done SiN passivation treatment. The maximum saturation current density () and maximum transconductance () increase as Lrecess decreases to 0.4m. At this time, the device shows mA/mm at V, V, and mS/mm at V, V. Meanwhile, as increases, it causes parasitic capacitance and to decrease, making drastically increases. When Lrecess=0.8m, the device shows GHz and GHz.
Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61434006). The authors would like to thank Yan-kui Li for his assistance during the measurements. We are also grateful to all the members of HighFrequency High-Voltage Device and Integrated Circuits Center for their valuable help during the experiment.
Corresponding Authors:
Peng Ding, Zhi Jin
E-mail: dingpeng@ime.ac.cn;jinzhi@ime.ac.cn
Cite this article:
Ruize Feng(封瑞泽), Bo Wang(王博), Shurui Cao(曹书睿), Tong Liu(刘桐), Yongbo Su(苏永波), Wuchang Ding(丁武昌), Peng Ding(丁芃), and Zhi Jin(金智) Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs 2022 Chin. Phys. B 31 018505
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