Impact of multiplexed reading scheme on nanocrossbar memristor memory’s scalability

doi:10.1088/1674-1056/23/2/028501

Abstract Nanocrossbar is a potential memory architecture to integrate memristor to achieve large scale and high density memory. However, based on the currently widely-adopted parallel reading scheme, scalability of the nanocrossbar memory is limited, since the overhead of the reading circuits is in proportion with the size of the nanocrossbar component. In this paper, a multiplexed reading scheme is adopted as the foundation of the discussion. Through HSPICE simulation, we reanalyze scalability of the nanocrossbar memristor memory by investigating the impact of various circuit parameters on the output voltage swing as the memory scales to larger size. We find that multiplexed reading maintains sufficient noise margin in large size nanocrossbar memristor memory. In order to improve the scalability of the memory, memristors with nonlinear I–V characteristics and high LRS (low resistive state) resistance should be adopted.

Keywords: nanocrossbar memristor multiplexing reading circuit voltage swing

Received: 04 June 2013
Revised: 27 June 2013
Accepted manuscript online:

PACS:	85.40.Bh	(Computer-aided design of microcircuits; layout and modeling)
	07.50.Ek	(Circuits and circuit components)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61003082).

Corresponding Authors: Wu Chun-Qing
E-mail: wuchunqing@nudt.edu.cn

About author: 85.40.Bh; 07.50.Ek

Cite this article:

Zhu Xuan (朱玄), Tang Yu-Hua (唐玉华), Wu Chun-Qing (吴纯青), Wu Jun-Jie (吴俊杰), Yi Xun (易勋) Impact of multiplexed reading scheme on nanocrossbar memristor memory’s scalability 2014 Chin. Phys. B 23 028501

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