New aspects of HCI test for ultra-short channel n-MOSFET devices
Ma Xiao-Hua(马晓华)a)b)†, Hao Yue(郝跃)a)b), Wang Jian-Ping(王剑屏)c), Cao Yan-Rong(曹艳荣)a)b), and Chen Hai-Feng(陈海峰)a)b)
a Microelectronics Institute, Xidian University, Xi'an 710071, China; b Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,Xidian University, Xi'an 710071, China; c Logic Technology Development Center, SMIC, Shanghai 201203, China
Abstract Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75--90 nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage ($V_{\rm d}$) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different $V_{\rm d}$ stresses in order to understand the relations between peak of substrate current ($I_{\rm sub}$) and channel length/stress voltage.
Received: 12 April 2006
Revised: 22 June 2006
Accepted manuscript online:
(Semiconductor-device characterization, design, and modeling)
Fund: Project supported by the National Natural Science Foundation of China (Grant No 60376024).
Cite this article:
Ma Xiao-Hua(马晓华), Hao Yue(郝跃), Wang Jian-Ping(王剑屏), Cao Yan-Rong(曹艳荣), and Chen Hai-Feng(陈海峰) New aspects of HCI test for ultra-short channel n-MOSFET devices 2006 Chinese Physics 15 2742
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