Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

doi:10.1088/1674-1056/23/7/078401

Abstract We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4× 0.46 mm². The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Keywords: phase-locked loop (PLL) fast locking time low spur complementary metal oxide semiconductor (CMOS)

Received: 29 October 2013
Revised: 30 December 2013
Accepted manuscript online:

PACS:	84.40.Lj	(Microwave integrated electronics)
	85.40.-e	(Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology)
	84.40.Dc	(Microwave circuits)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61307128), the National Basic Research Program of China (Grant No. 2010CB327505), the Specialized Research Found for the Doctoral Program of Higher Education of China (Grant No. 20131101120027), and the Basic Research Foundation of Beijing Institute of Technology of China (Grant No. 20120542015).

Corresponding Authors: Si Li-Ming
E-mail: lms@bit.edu.cn

About author: 84.40.Lj; 85.40.-e; 84.40.Dc

Cite this article:

Zhu Si-Heng (朱思衡), Si Li-Ming (司黎明), Guo Chao (郭超), Shi Jun-Yu (史君宇), Zhu Wei-Ren (朱卫仁) Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process 2014 Chin. Phys. B 23 078401

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Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

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